參數(shù)資料
型號(hào): 28F160C18
廠商: Intel Corp.
英文描述: 1.8V Advanced+ Boot Block Flash Memory(1.8V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 1.8高級(jí)啟動(dòng)塊閃存(1.8V的高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
文件頁(yè)數(shù): 8/52頁(yè)
文件大?。?/td> 272K
代理商: 28F160C18
28F160C18
E
8
ADVANCE INFORMATION
Table 2. 1.8 Volt Advanced+ Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
19
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
16-Mbit x 16: A[0-19]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, configuration and status register data.
The data pins float to tri-state when the chip is de-selected or the outputs
are disabled.
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and configuration data. The data pins float to tri-state when
the chip is de-selected.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and
memory array. WE# is active low. Addresses and data are latched on
the rising edge of the second WE# pulse.
RST#
INPUT
RESET:
Uses two voltage levels (V
IL
, V
IH
) to control reset mode.
When RST# is at logic low, the device is in reset
which drives the
outputs to High-Z and resets the Write State Machine.
When RST# is at logic high, the device is in standard operation
.
When RST# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT:
Controls the lock-down function of the flexible
Locking feature
When WP# is a logic low, the lock-down mechanism is enabled
and
blocks marked lock-down cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled
and
blocks previously locked-down are now locked and can be unlocked and
locked through software. After WP# goes low, any blocks previously
marked lock-down revert to that state.
See Section 3.3 for details on block locking.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
[1.65 V–1.95 V] Supplies power for device
operations.
V
CCQ
INPUT
I/O POWER SUPPLY:
Supplies power for input/output buffers.
[1.65 V–1.95 V] This input should be tied directly to V
CC
.
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