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參數資料
| 型號： | 28F160C18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導塊閃速存儲器) |
| 中文描述： | 1.8高級啟動塊閃存（1.8V的高級引導塊閃速存儲器） |
| 文件頁數： | 24/52頁 |
| 文件大小： | 272K |
| 代理商： | 28F160C18 |
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28F160C18
E
24
ADVANCE INFORMATION
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
3.7
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since
the
device is indifferent as to which power supply, V
PP
or V
CC
, powers-up first.
3.7.1
RST# CONNECTED TO SYSTEM
RESET
The use of RST# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RST# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when V
CC
voltages are above V
LKO
. Since
both WE# and CE# must be low for a command
write, driving either signal to V
IH
will
inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the two-
step command sequences. The device is also
disabled until RST# is brought to V
IH
, regardless of
the state of its control inputs. By holding the device
in reset (RST# connected to system PowerGood)
during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another
level of memory protection.
3.7.2
V
CC
, V
PP
AND RST# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after V
CC
transitions above V
LKO
(Lockout voltage), is read
array mode.
After any program or block erase operation is
complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
3.8
Power Supply Decoupling
Flash memory’s power switching characteristics
require
careful
device
designers should consider three supply current
issues:
1.
Standby current levels (I
CCS
)
2.
Read current levels (I
CCR
)
3.
Transient peaks produced by falling and rising
edges of CE#.
decoupling.
System
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
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