參數(shù)資料
型號: 28F160C18
廠商: Intel Corp.
英文描述: 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導塊閃速存儲器)
中文描述: 1.8高級啟動塊閃存(1.8V的高級引導塊閃速存儲器)
文件頁數(shù): 5/52頁
文件大?。?/td> 272K
代理商: 28F160C18
E
1.0
28F160C18
5
ADVANCE INFORMATION
INTRODUCTION
This document contains the specifications for the
Intel
1.8 Volt Advanced+ Boot Block flash memory
family, which is optimized for low power, portable
systems. This family of products features a low
V
CC
/V
PP
operating range 1.65 V
–1.95 V for read,
program, and erase operations. In addition this
family is capable of fast programming at 12 V.
Throughout this document, the term “1.65 V” refers
to the full voltage range 1.65 V–1.95 V (except
where noted otherwise) and “V
PP
= 12 V” refers to
12 V ±5%. Section 1 and 2 provides an overview of
the flash memory family including applications,
pinouts, pin descriptions and memory organization.
Section 3 describes the operation of these products
and Section 4 contains electrical specifications.
Finally, Section 5 contains ordering information.
1.1
1.8 Volt Advanced+ Boot Block
Flash Memory Enhancements
The 1.8 Volt Advanced+ Boot Block flash memory
features:
Zero-latency, flexible block locking
128-bit Protection Register
Simple
system
implementation
production programming with 1.65 V in-field
programming
Ultra-low power operation at 1.65 V
Minimum 100,000 block erase cycles
Common Flash Interface for software query of
device specs and features
for
12 V
Table 1. 1.8 Volt Advanced+ Boot Block Feature Summary
Feature
16 Mbit
Reference
V
CC
Operating Voltage
1.65 V – 1.95 V
Table 10
V
PP
Voltage
Provides complete write protection with
optional 12 V Fast Programming
Table 10
V
CCQ
I/O Voltage
1.65 V – 1.95 V
Bus Width
16-bit
Speed (ns)
90, 120 ns @ 1.65 V
Section 4.5
Blocking (top or bottom)
8 x 4-KW parameter
16-Mb: 31 x 32-KW main
Section 2.2
Appendix E
Operating Temperature
Extended: –40 °C to +85 °C
Table 10
Program/Erase Cycling
100,000 cycles (minimum)
Table 10
Packages
48-Lead TSOP
55-Ball
μ
BGA* CSP
Figures 1, 2
Block Locking
Flexible locking of any block with zero latency
Section 3.3
Protection Register
64-bit unique device number, 64-bit user programmable
Section 3.4
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