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參數(shù)資料
| 型號： | 28F160C18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導(dǎo)塊閃速存儲器) |
| 中文描述： | 1.8高級啟動塊閃存（1.8V的高級引導(dǎo)塊閃速存儲器） |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F160C18 |
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28F160C18
E
10
ADVANCE INFORMATION
Table 3. Bus Operations
Mode
Note
RST#
CE#
OE#
WE#
DQ
0
–15
Read (Array, Status,
Configuration, or Query)
2,3
V
IH
V
IL
V
IL
V
IH
D
OUT
Output Disable
1
V
IH
X
V
IH
X
High Z
Standby
1
V
IH
V
IH
X
X
High Z
Reset
1,5
V
IL
X
X
X
High Z
Write
4,5
V
IH
V
IL
V
IH
V
IL
D
IN
NOTES:
1.
2.
3.
4.
5.
X must be V
IL
, V
IH
for control pins and addresses.
See DC Characteristicsfor V
PPLK
, V
PP1
and V
PP2
voltages.
Manufacturer and device codes may also be accessed in read configuration mode (A
1
–A
19
= 0). See Table 4.
Refer to Table 5 for valid D
IN
during a write operation.
To program or erase the lockable blocks, hold WP# at V
IH
.
3.1.1
READ
The flash memory has four read modes available:
read array, read configuration, read status and read
query. These modes are accessible independent of
the V
voltage. The appropriate read mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RST# must be at V
IH
. Figure 7
illustrates a read cycle.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (V
), the device
outputs are disabled. Output pins are placed in a
high-mpedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (V
) places the device in standby mode,
which
substantially
reduces
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
device
power
3.1.4
RESET
From read mode, RST# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a
high-mpedance state, and turns off all internal
circuits. After return from reset, a time t
PHQV
is
required until the initial read access outputs are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, the
status register is set to 80H, and all blocks are
locked. This case is shown in Figure 9A.
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