參數(shù)資料
型號(hào)： 28F160C18
廠商： Intel Corp.
英文描述： 1.8V Advanced+ Boot Block Flash Memory(1.8V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 1.8高級(jí)啟動(dòng)塊閃存（1.8V的高級(jí)引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 16/52頁(yè)
文件大小： 272K
代理商： 28F160C18
28F160C18
E
16
ADVANCE INFORMATION
Table 6. Command Codes and Descriptions
Code
Device Mode
Description
FF
Read Array
Places device in read array mode, such that array data will be output on the
data pins.
40
Program
Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.5.
20
Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a
“1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.6.
D0
Erase Confirm
Program/Erase
Resume
Unlock Block
If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. During program/erase, the device will respond only to the Read
Status Register, Program Suspend and Erase Suspend commands and will
output status register data when CE# or OE# is toggled.
If a program or erase operation was previously suspended, this command will
resume that operation.
If the previous command was Configuration Set-Up, the CUI will latch the
address and unlock the block indicated on the address pins. If the block had
been previously set to Lock-Down, this operation will have no effect. (Sect. 3.3)
B0
Program
Suspend
Erase
Suspend
Issuing this command will begin to suspend the currently executing
program/erase operation. The status register will indicate when the operation
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RST#, which will immediately shut down the WSM and
the remainder of the chip if RST# is driven to V
IL
. See Sections 3.2.5.1 and
3.2.6.1.
70
Read Status
Register
This command places the device into read status register mode. Reading the
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
50
Clear Status
Register
The WSM can set the Block Lock Status (SR.1) , V
PP
Status (SR.3), Program
Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90
Read
Configuration
Puts the device into the Read Configuration mode, so that reading the device
will output the manufacturer/device codes or block lock status. Section 3.2.2.
60
Configuration
Set-Up
Prepares the CUI for changes to the device configuration, such as block locking
changes. If the next command is not Block Unlock, Block Lock, or Block Lock-
Down, then the CUI will set both the Program and Erase Status register bits to
indicate a command sequence error. See Section 3.3.
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