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| 型號(hào)： | 1893YI-10 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, INTERFACE CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, TQFP-64 |
| 文件頁(yè)數(shù)： | 72/152頁(yè) |
| 文件大?。?/td> | 943K |
| 代理商： | 1893YI-10 |
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ICS1893 Rev C 6/6/00
June, 2000
26
Chapter 6
Interface Overviews
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
6.1
MII Data Interface
The most common configuration for an ICS1893’s MAC/Repeater Interface is the Medium Independent
Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893 MAC/Repeater Interface is
configured for the MII Data Interface mode, data is transferred between the PHY and the MAC/repeater as
framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to
synchronize the transfers.
The ICS1893 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit
and a receive data path to synchronously exchange 4 bits of data (that is, nibbles).
The ICS1893’s MII transmit data path includes the following:
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
The ICS1893’s MII receive data path includes the following:
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by
the ICS1893 (that is, the ICS1893 sources the TXCLK and RXCLK signals to the MAC/repeater).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICs1893 is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
Half-duplex mode, the ICS1893 asserts the Carrier Sense signal when data is being either transmitted or
received. While operating in half-duplex mode, the ICS1893 also asserts its Collision Detect signal to
indicate that data is being received while a transmission is in progress.
Full-duplex mode, the ICS1893 asserts the Carrier Sense signal only when receiving data and forces the
Collision Detect signal to remain inactive.
As mentioned in Section 5.1.1.3, “Hot Insertion”, the ICS1893 design allows hot insertion of its MII. That is,
it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1893 isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit pins
(TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1893
enables its MII and enables its Twisted-Pair Transmit signals.
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| 1893YI-10LF | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 1893YI-10LFT | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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