參數(shù)資料
型號： 1893YI-10
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡接口
英文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, TQFP-64
文件頁數(shù)： 66/152頁
文件大?。?/td> 943K
代理商： 1893YI-10
ICS1893 Rev C 6/6/00
June, 2000
20
Chapter 5
Operating Modes Overview
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
5.1
Reset Operations
This section first discusses reset operations in general and then specific ways in which the ICS1893 can be
configured for various reset options.
5.1.1
General Reset Operations
The following reset operations apply to all the specific ways in which the ICS1893 can be reset, which are
discussed in Section 5.1.2, “Specific Reset Operations”.
5.1.1.1
Entering Reset
When the ICS1893 enters a reset condition (either through hardware, power-on reset, or software), it does
the following:
1.
Isolates the MAC/Repeater Interface input pins
2.
Drives all MAC/Repeater Interface output pins low
3.
Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
4.
Initializes all its internal modules and state machines to their default states
5.
Enters the power-down state
6.
Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
Register bits to their default values
5.1.1.2
Exiting Reset
When the ICS1893 exits a reset condition, it does the following:
1.
Exits the power-down state
2.
Latches the Serial Management Port Address of the ICS1893 into the Extended Control Register, bits
16.10:6. [See Section 8.11.3, “PHY Address (bits 16.10:6)”.]
3.
Enables all its internal modules and state machines
4.
Sets all Management Register bits to either (1) their default values or (2) the values specified by their
associated ICS1893 input pins, as determined by the HW/SW pin
5.
Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
6.
Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
(TXCLK) and receive clock (RXCLK)
7.
Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
is removed
5.1.1.3
Hot Insertion
As with the ICS189X products, the ICS1893 reset design supports ‘hot insertion’of its MII. (That is, the
ICS1893 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the
MAC/repeater.)
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PDF描述
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