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參數(shù)資料
| 型號(hào)： | ZL50408GDG2 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208 |
| 文件頁(yè)數(shù)： | 90/144頁(yè) |
| 文件大?。?/td> | 1779K |
| 代理商： | ZL50408GDG2 |
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ZL50408
Data Sheet
5
Zarlink Semiconductor Inc.
January 2005
Updated GMII timing (13.4.11, “Gigabit Media Independent Interface (GMII)“ on page 139)
reduce min. hold time from 1ns to 0.5ns
reduced max. output delay by 1ns
Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
June 2005
Clarified that port mirroring is only available if the source & destination ports are in RMII mode
Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F
Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap
TSTOUT[0]
Added power sequencing recommendation (1.7, “Power Sequencing“ on page 26)
Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface
Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50408 (11.0, “Hardware Statistics
December 2005
Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,
Added more text to section 2.8, “JTAG“ on page 29
Clarified counter definitions (11.0, “Hardware Statistics Counters“ on page 54)
Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]
Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and
this bit was mistakenly left in the register definition.
April 2006
Added Pb-free order code (ZL50408GDG2)
Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)
since it wasn’t really discussed in the DS
Clarified registers UCC, MCC & MCCTH
Renamed register UCC (now PCC), as name was misleading
Updated timing to CPU RvMII, as min. output delay should have been 0 ns
July 2006
Added typical values to power numbers in “Recommended Operating Conditions” table.
Updated RM6 “CPU_MII_TXEN Output Delay Time” & RM7 “CPU_MII_TXD[3:0] Output Delay Time” max. to
5 ns (old 14 ns)
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相關(guān)代理商/技術(shù)參數(shù) |
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| ZL50409 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
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| ZL50410 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
| ZL50410GDC208 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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