參數(shù)資料
型號(hào): ZL50408GDG2
廠商: CONEXANT SYSTEMS
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁(yè)數(shù): 67/144頁(yè)
文件大?。?/td> 1779K
代理商: ZL50408GDG2
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)當(dāng)前第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)
ZL50408
Data Sheet
29
Zarlink Semiconductor Inc.
2.8
JTAG
An IEEE1149.1 compliant test interface is provided for boundary scan. The JTAG interface, collectively known as a
Test Access Port, or TAP, uses the following signals to support the operation of boundary scan:
TCK – the TCK or ‘test clock’ synchronizes the internal state machine operations
TMS – the TMS or ‘test mode state’ is sampled at the rising edge of TCK to determine the next state
TDI – the TDI or ‘test data in’ represents the data shifted into the device’s test or programming logic. It is
sampled at the rising edge of TCK when the internal state machine is in the correct state
TDO – the TDO or ‘test data out’ represents the data shifted out of the device’s test or programming logic
and is valid on the falling edge of TCK when the internal state machine is in the correct state
TRST – the TRST or ‘test reset’ is an optional pin which, when available, can reset the TAP controller’s state
machine
2.8.1
Registers
There are two types of registers associated with boundary scan. Each compliant device has one instruction register
and two or more data registers.
Instruction Register – the instruction register holds the current instruction. Its content is used by the TAP
controller to decide what to do with signals that are received. Most commonly, the content of the instruction
register will define to which of the data registers signals should be passed.
Data Registers – there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS
register and the IDCODES register. Other data registers may be present, but they are not required as part of
the JTAG standard.
BSR – this is the main testing data register. It is used to move data to and from the ‘pins’ on a device.
BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in
a circuit to be tested with minimal overhead.
IDCODES – this register contains the ID code and revision number for the device. This information allows
the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of
the Boundary Scan configuration for the device.
2.8.2
Test Access Port (TAP) Controller
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the behaviour of
the JTAG system. For more detail on each state, refer to the IEEE 1149.1 Standard JTAG document.
2.8.3
Boundary Scan Instructions
The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered
compliant. These instructions are:
BYPASS – the BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit
pass-through register (the BYPASS register). This instruction allows the testing of other devices in the JTAG
chain without any unnecessary overhead.
EXTEST – the EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register
(BSR). The device’s pin states are sampled with the ‘capture dr’ JTAG state and new values are shifted into
the BSR with the ‘shift dr’ state; these values are then applied to the pins of the device using the ‘update dr’
state.
SAMPLE/PRELOAD – the SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the
BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be
accessed by a data scan operation to take a sample of the functional data entering and leaving the device.
The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction.
相關(guān)PDF資料
PDF描述
ZL50418GKG2 DATACOM, LAN SWITCHING CIRCUIT, PBGA553
ZL50418/GKC DATACOM, LAN SWITCHING CIRCUIT, PBGA553
ZL50418GKG2 DATACOM, LAN SWITCHING CIRCUIT, PBGA553
ZLW-2-B 1 MHz - 1000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 9.5 dB CONVERSION LOSS-MAX
ZMG71W SINGLE COLOR LED, GREEN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50409 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch
ZL50409GDC 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch
ZL50409GDC1 制造商:Microsemi Corporation 功能描述:
ZL50410 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch
ZL50410GDC208 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch