參數(shù)資料
型號(hào)： ZL50408GDG2
廠商： CONEXANT SYSTEMS
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁數(shù)： 121/144頁
文件大?。?/td> 1779K
代理商： ZL50408GDG2
ZL50408
Data Sheet
78
Zarlink Semiconductor Inc.
12.3.1.3
ECR3Pn: Port n Control Register
IC Address: h014+n; CPU Address: h0080+2n (n = port number)
Accessed by CPU and IC (R/W)
12.3.1.4
ECR4Pn: Port n Control Register
IC Address: h01E+n; CPU Address: h0081+2n (n = port number)
Accessed by CPU and IC (R/W)
Port 0 – 7: (RMAC Ports)
Bit [0]:
Enable receiving short frame < 64B
0: Disable (Default)
1: Allow receiving short frame with correct CRC.
Bit [1]:
Enable receiving long frame > 1522
0: Disable (Default)
1: Allow receiving long frame that are <= BUF_LIMIT value
Bit [2]:
Enable pad frame to 64B when transmitted
0: Allow padding to 64B (Default)
1: Disable
Bit [3]:
Enable compress preamble
0: Send standard preamble (Default)
1: Only one byte preamble+SFD
Bits [6:4]
Number of bytes removed from the Inter-Frame Gap (IFG). (Default 0x0)
Bit [7]
Link Heart Beat Transmit (RMAC ports only)
0: Disable (Default)
1: Enable
Bit [1:0]:
Enable PHY Mode
00: MAC Mode (Default)
11: PHY Mode (Reverse MII/GPSI)
Only valid in MII and GPSI interface modes. In PHY mode, Mn_TXCLK &
Mn_RXCLK pins becomes outputs.
Bit [2]:
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Bits [4:3]:
Interface mode:
00 - GPSI mode
01 - MII mode
10 - Reserved
11 - RMII mode (Default)
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