參數(shù)資料
型號(hào)： ZL50408GDG2
廠商： CONEXANT SYSTEMS
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁(yè)數(shù)： 19/144頁(yè)
文件大小： 1779K
代理商： ZL50408GDG2
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ZL50408
Data Sheet
115
Zarlink Semiconductor Inc.
12.3.9.11
QOSC16 - QOSC21 - Classes Byte Limit CPU port
I2C Address: h088-08D; CPU Address: h0890-0895
Accessed by CPU and I2C (R/W):
QOSC16 – Port 8 (CPU) L1 threshold for queue 1
QOSC17 – Port 8 (CPU) L2 threshold for queue 1
QOSC18 – Port 8 (CPU) L1 threshold for queue 2
QOSC19 – Port 8 (CPU) L2 threshold for queue 2
QOSC20 – Port 8 (CPU) L1 threshold for queue 3
QOSC21 – Port 8 (CPU) L2 threshold for queue 3
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.12
QOSC22 - QOSC27 - Classes Byte Limit GMAC port
IC Address: h08E-08F; CPU Address: h0896-089B
Accessed by CPU and IC (R/W)
QOSC22 – Port 9 (uplink) L1 threshold for queue 1
QOSC23 – Port 9 (uplink) L2 threshold for queue 1
QOSC24 – Port 9 (uplink) L1 threshold for queue 2
QOSC25 – Port 9 (uplink) L2 threshold for queue 2
QOSC26 – Port 9 (uplink) L1 threshold for queue 3
QOSC27 – Port 9 (uplink) L2 threshold for queue 3
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue
size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the
queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.13
QOSC28 - QOSC31 - Classes WFQ Credit For GMAC
CPU Address: h089C-089F
Accessed by CPU (R/W)
QOSC28 – CREDIT_C00
QOSC29 – CREDIT_C01
QOSC30 – CREDIT_C02
QOSC31 – CREDIT_C03
Bits [5:0] in QOSC28 through QOSC31 represents one set of WFQ parameters for GMAC port. The granularity of
the numbers is 1, and their sum must be 64. QOSC31 corresponds to queue 3, that is the highest priority, and
QOSC27 corresponds to queue 0.
Default scheduling method will be strict priority across all queues. Only when the bit [7] is set, the queue will be
scheduled as WFQ. The credit number also works as shaper credit if bit [6] is set. A queue with shaper enabled will
be scheduled by strict priority when the token is available. The shaper setting override the WFQ (bit [7]) setting.
Bits [5:0]:
Class scheduling credit
Bit [6]:
Traffic Shaper Enable
0: Disable
1: Enable
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參數(shù)描述
ZL50409 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch
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ZL50409GDC1 制造商:Microsemi Corporation 功能描述:
ZL50410 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch
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