參數(shù)資料
型號： ZL50408GDG2
廠商： CONEXANT SYSTEMS
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁數(shù)： 110/144頁
文件大?。?/td> 1779K
代理商： ZL50408GDG2
ZL50408
Data Sheet
68
Zarlink Semiconductor Inc.
MIRROR_SRC_MAC5
Mirror Source MAC
Address 5
070B
R/W
NA
00
MIRROR_CONTROL
Port Mirror Control Register
070C
R/W
NA
00
RMII_MIRROR0
RMII Mirror 0
0710
R/W
NA
00
RMII_MIRROR1
RMII Mirror 1
0711
R/W
NA
00
8. Per Port QOS Control
FCRn
Flooding Control Register n
0800+n
R/W
04C+n
00
(n=0..9)
BMRCn
Broadcast/Multicast Rate
Control n
0820+n
R/W
05E+n
00
PR100_n
Port Reservation for RMAC
Ports (n=0..7)
0840+n
R/W
06A+n
06
‘d1536/1
6=‘d96,
‘d96>>4=
’h6
PR100_CPU
Port Reservation for CPU
Port
0848
R/W
073
06
‘d96
PRG
Port Reservation for GMAC
Port
0849
R/W
072
24
‘d96x6=‘d
576,
‘d576>>4
=’h24
PTH100_n
Port Threshold for RMAC
Ports (n=0..7)
0860+n
R/W
0C2+n
03
PTH100_CPU
Port Threshold for CPU
Port
0868
R/W
0CB
03
PTHG
Port Threshold for GMAC
Port
0869
R/W
0CA
12
QOSCn
QOS Control n
0880+n
R/W
078-08F
00
(n=0..39)
NA
E. System Diagnostic
DTSRL
Test Register Low
0E00
R/W
NA
00
DTSRM
Test Register Medium
0E01
R/W
NA
01
TESTOUT0
Testmux Output [7:0]
0E02
R/O
NA
TESTOUT1
Testmux Output [15:8]
0E03
R/O
NA
MASK0
MASK Timeout 0
0E10
R/W
0F6
00
MASK1
MASK Timeout 1
0E11
R/W
0F7
00
MASK2
MASK Timeout 2
0E12
R/W
0F8
00
MASK3
MASK Timeout 3
0E13
R/W
0F9
00
MASK4
MASK Timeout 4
0E14
R/W
0FA
00
Register
Description
CPU Addr
(Hex)
R/W
IC
Addr
(Hex)
Default
(Hex)
Notes
Table 12 - Register Description (continued)
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