參數(shù)資料
型號(hào): ZL50408GDG2
廠商: CONEXANT SYSTEMS
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁(yè)數(shù): 125/144頁(yè)
文件大?。?/td> 1779K
代理商: ZL50408GDG2
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ZL50408
Data Sheet
81
Zarlink Semiconductor Inc.
12.3.2
(Group 1 Address) VLAN Group
12.3.2.1
AVTCL – VLAN Type Code Register Low
IC Address: h028; CPU Address: h0100
Accessed by CPU and IC (R/W)
12.3.2.2
AVTCH – VLAN Type Code Register High
IC Address: h029; CPU Address: h0101
Accessed by CPU and IC (R/W)
12.3.2.3
PVMAP00_0 – Port 0 Configuration Register 0
IC Address: h02A, CPU Address: h0102
Accessed by CPU and IC (R/W)
In Port Based VLAN Mode
This register indicates the legal egress ports. A “1” on bit 3 means that the packet can be sent to port 3. A “0” on bit
3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit
mask to all egress ports.
In Tag based VLAN Mode
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default VLAN tag.
If the received packet is untagged, then the packet is classified with the default VLAN tag. If the received packet has
a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
12.3.2.4
PVMAP00_1 – Port 0 Configuration Register 1
IC Address: h034, CPU Address: h0103
Accessed by CPU and IC (R/W)
In Port based VLAN Mode
Bits [7:3]:
Reserved
Bits [7:0]:
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00)
Bits [7:0]:
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
Bits [7:0]:
VLAN Mask for port 0 (Default 0xFF)
Bits [7:0]:
PVID [7:0] (Default is 0xFF)
Bits [1:0]:
VLAN Mask for ports 9 to 8 (Default 0x3)
Bits [7:2]:
Reserved (Default 0x3F)
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