參數(shù)資料
型號(hào): ZL50408GDG2
廠商: CONEXANT SYSTEMS
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁數(shù): 54/144頁
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
17
Zarlink Semiconductor Inc.
System Clock, Power, and Ground Pins
A1
SCLK
Input
System Clock. Based on system requirement,
SCLK needs to operate at difference
frequency.
SCLK requires 40/60% duty cycle clock.
D9, H4, H13, N7,
VDD
Power
+1.8 Volt DC Supply
D5, D12, E4, E13, M4,
M13, N5,
VCC
Power
+3.3 Volt DC Supply
G7-10, H7-10, J7-10,
K7-10
VSS
Power Ground
Ground
Misc.
D1
RESIN#
Input
Reset Input
C1
RESETOUT#
Output
Reset PHY
F1
M_MDC
Output
MII Management Data Clock
F2
M_MDIO
I/O-TS
with pull-up
MII Management Data I/O
R7
M_CLK
Input
RMAC Reference Clock
A13
GREF_CLK
Input
with pull-up
GMAC Reference Clock
D6
IC_GND
Internal Connect. Tie to ground (VSS) via 1 K
resistor.
Bootstrap Pins1
External pull-up/down resistors are required on all bootstrap pins for proper operation. See “Bootstrap Options” on
page 23 for more information.
D2
TSTOUT[0]
Input (Reset Only)
Enable Debounce on SSI interface
Pullup – Enabled
Pulldown - Disabled
When enabled, DATAOUT is an open-drain
output; when disabled, DATAOUT is a
totem-pole output.
page 132 for more details on debounce
timing.
Ball Signal Description Table (continued)
Ball No(s)
Symbol
I/O
Description
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