參數(shù)資料
型號: ZL50408GDG2
廠商: CONEXANT SYSTEMS
元件分類: 網(wǎng)絡接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁數(shù): 20/144頁
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
116
Zarlink Semiconductor Inc.
12.3.9.14
QOSC36 - QOSC39 - Shaper Control Port GMAC
CPU Address: h08A4-08A7
Accessed by CPU (R/W)
QOSC36 – TOKEN_LIMIT_C00
QOSC37 – TOKEN_LIMIT_C01
QOSC38 – TOKEN_LIMIT_C02
QOSC39 – TOKEN_LIMIT_C03
QOSC36 through QOSC39 represents one set of token limit on the shaper of GMAC port. The granularity of the
numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the
hardware implementation can keep negative number, the limit can be as small as one and still can transmit
oversized frame, as long as one byte token is available.
12.3.10
(Group E Address) System Diagnostic
NOTE: Device Manufacturing test registers.
12.3.10.1
DTSRL – Test Output Selection
CPU Address: h0E00
Accessed by CPU (R/W)
Test group selection for testout[7:0].
12.3.10.2
DTSRM – Test Output Selection
CPU Address: h0E01
Accessed by CPU (R/W)
Test group selection for testout[15:8].
12.3.10.3
TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8]
CPU Address: h0E02-0E03
Accessed by CPU (RO)
12.3.10.4
MASK0-MASK4 – Timeout Reset Mask
CPU Address: h0E10-E14
Accessed by CPU (R/W)
Disable timeout reset on selected state machine status.
See Programming Timeout Reset application note, ZLAN-41, for more information.
Bit [7]:
Enable WFQ Scheduling
0: Strict Priority
1: WFQ
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