參數(shù)資料
型號(hào): ZL50408GDG2
廠(chǎng)商: CONEXANT SYSTEMS
元件分類(lèi): 網(wǎng)絡(luò)接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁(yè)數(shù): 132/144頁(yè)
文件大?。?/td> 1779K
代理商: ZL50408GDG2
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ZL50408
Data Sheet
88
Zarlink Semiconductor Inc.
12.3.4.6
MAC5 – CPU MAC address byte 5
CPU Address: h0305
Accessed by CPU (R/W)
12.3.4.7
INT_MASK0 – Interrupt Mask
CPU Address: h0306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
- 1: Mask the interrupt
- 0: Unmask the interrupt (Enable interrupt) (Default)
12.3.4.8
INTP_MASK0 – Interrupt Mask for MAC Port 0,1
CPU Address: h0310
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)
- 1: Mask the interrupt
- 0: Unmask the interrupt (Default)
Bits [7:0]:
Byte 5 (bits [47:40]) of the CPU MAC address (Default 0)
Note: Bits [42:40] are set on a per port basis using MAC01, MAC23, MAC45,
MAC67 registers. For port 9, this register is ignored and MAC9 is used for bits
[47:40].
Bit [0]:
CPU frame interrupt. CPU frame buffer has data for CPU to read
Bit [1]:
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Bit [2]:
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Bits [6:3]:
Reserved
Bit [7]:
Device Timeout Detected interrupt
Bit [0]:
Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources
Bit [1]:
Port 0 link change mask
Bit [2]:
Port 0 module detect mask
Bit [3]:
Reserved
Bit [4]:
Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources.
Bit [5]:
Port 1 link change mask
Bit [6]:
Port 1 module detect mask
Bit [7]
Reserved
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