參數(shù)資料
型號： ZL50408GDG2
廠商： CONEXANT SYSTEMS
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封裝： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件頁數(shù)： 142/144頁
文件大?。?/td> 1779K
代理商： ZL50408GDG2
ZL50408
Data Sheet
97
Zarlink Semiconductor Inc.
12.3.6.11
C3RS – Class 3 Reserve Size
IC Address: h077; CPU Address: h051B
Accessed by CPU and IC (R/W)
Buffer reservation for class 3. Granularity 16 granules. (Default 0)
12.3.6.12
AVPML – VLAN Tag Priority Map
IC Address: h056; CPU Address: h0530
Accessed by CPU and IC (R/W)
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit
priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature
allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0
of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used
inside the ZL50408. When the packet goes out it carries the original priority.
12.3.6.13
AVPMM – VLAN Priority Map
IC Address: h057; CPU Address: h0531
Accessed by CPU and IC (R/W)
Map VLAN priority into eight level transmit priorities:
Bits [7:0]:
Class 3 FCB Reservation
Bits [2:0]:
Priority when the VLAN tag priority field is 0 (Default 0)
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
...
Transmit Priority Level 6
Transmit Priority Level 7 (Highest)
Bits [5:3]:
Priority when the VLAN tag priority field is 1 (Default 0)
Bits [7:6]:
Priority when the VLAN tag priority field is 2 (Default 0)
Bit [0]:
Priority when the VLAN tag priority field is 2 (Default 0)
Bits [3:1]:
Priority when the VLAN tag priority field is 3 (Default 0)
Bits [6:4]:
Priority when the VLAN tag priority field is 4 (Default 0)
Bit [7]:
Priority when the VLAN tag priority field is 5 (Default 0)
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