參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 88/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
88
T
ABLE
98:
T
X
CP OAM R
EGISTER
R
EGISTER
97 T
X
CP OAM R
EGISTER
H
EX
A
DDRESS
: 0
X
61
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Send OAM
Sem
0
A “0” to “1” transitions configures the Transmit Cell Processor to transmit an
OAM cell.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
6
Tx CRC10 Enable
R/W
0
0: OAM Cell CRC-10 Calculation and Insertion are disabled.
1: OAM Cell CRC-10 Calculation and Insertion is enabled. The Transmit
Cell Processor will compute and insert the CRC-10 value within each “out-
bound” OAM cell.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
5-0
Unused
RO
0x00
T
ABLE
99:
T
X
CP HEC E
RROR
M
ASK
R
EGISTER
R
EGISTER
98 T
X
CP HEC E
RROR
M
ASK
R
EGISTER
H
EX
A
DDRESS
: 0
X
62
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
HEC Error Mask
R/W
0x00
The Transmit Cell Processor block always XORs contents of this register with
the contents of the HEC byte (within each “outbound” ATM cell). This
“XORed” value is then written back into the “HEC” byte field, within each
“outbound” ATM cell; prior to transmission. Setting any of these bit-fields to
“1” introduces error in that specific bit, within each “outbound” HEC byte.
Register must be set to 0x00 for normal operation,
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
T
ABLE
100:
F
UTURE
U
SE
R
EGISTER
99 F
UTURE
U
SE
H
EX
A
DDRESS
: 0
X
63
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
T
ABLE
101:
T
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-1
R
EGISTER
100 T
X
CP I
DLE
C
ELL
P
ATTERN
H
EADER
B
YTE
-1 H
EX
A
DDRESS
: 0
X
64
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
Tx Idle Cell Pattern 1
R/W
0x00
Contains pattern for the first header byte of each “outbound” idle cell.
Register is set to 0x00 when transmitting standard idle cell pattern.
N
OTE
:
This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
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