參數(shù)資料
型號(hào)： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 102/104頁
文件大小： 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER IC
á
PRELIMINARY
REV. P1.0.5
102
edge of RxLineClk) ....................................................................................................................... 40
Figure 12. Receive DS3 Framer Line Interface Input Signal Timing (RxPOS and RxNEG are sampled on the
falling edge of RxLineClk) ............................................................................................................. 41
Figure 13. Receive PLCP Processor—POH Byte Serial Output Port Interface Timing .................................. 41
Figure 14. GFC Nibble-Field Serial Output Port Timing (Receive Cell Processor) ......................................... 42
Figure 15. Receive UTOPIA Interface Block Timing ....................................................................................... 42
Figure 16. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ........................ 43
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ........................ 43
Figure 18. Microprocessor Interface Timing—Motorola Type Processors (Read Operations) Non-Burst Mode .
44
Figure 19. Microprocessor Interface Timing—Motorola Type Processor (Write Operations) Non-Burst Mode ...
44
Figure 20. Microprocessor Interface Timing - Reset Pulse Width ................................................................... 44
LIST OF REGISTERS ....................................................................................................... 45
R
EGISTER
SUMMARY
L
IST
.......................................................................................................................... 45
T
ABLE
1: UNI O
PERATING
M
ODE
R
EGISTER
...................................................................................................... 47
T
ABLE
2: UNI I/O C
ONTROL
R
EGISTER
.............................................................................................................. 48
T
ABLE
3: P
ART
N
UMBER
R
EGISTER
................................................................................................................... 48
T
ABLE
4: V
ERSION
N
UMBER
R
EGISTER
.............................................................................................................. 48
T
ABLE
5: UNI I
NTERRUPT
E
NABLE
R
EGISTER
..................................................................................................... 49
T
ABLE
6: UNI I
NTERRUPT
S
TATUS
R
EGISTER
..................................................................................................... 50
T
ABLE
7: T
EST
C
ELL
C
ONTROL
AND
S
TATUS
R
EGISTER
..................................................................................... 51
T
ABLE
8: T
EST
C
ELL
E
RROR
A
CCUMULATOR
H
OLDING
R
EGISTER
....................................................................... 52
T
ABLE
9: T
EST
C
ELL
H
EADER
B
YTE
-1 ............................................................................................................... 52
T
ABLE
10: T
EST
C
ELL
H
EADER
B
YTE
-2 ............................................................................................................. 52
T
ABLE
11: T
EST
C
ELL
H
EADER
B
YTE
-3 ............................................................................................................. 52
T
ABLE
12: T
EST
C
ELL
H
EADER
B
YTE
-4 ............................................................................................................. 52
T
ABLE
13: T
EST
C
ELL
E
RROR
A
CCUMULATOR
- MSB ........................................................................................ 53
T
ABLE
14: T
EST
C
ELL
E
RROR
A
CCUMULATOR
- LSB ......................................................................................... 53
T
ABLE
15: R
X
DS3 C
ONFIGURATION
AND
S
TATUS
R
EGISTER
............................................................................. 54
T
ABLE
16: R
X
DS3 S
TATUS
R
EGISTER
............................................................................................................... 55
T
ABLE
17: R
X
DS3 I
NTERRUPT
E
NABLE
R
EGISTER
............................................................................................ 55
T
ABLE
18: R
X
DS3 I
NTERRUPT
S
TATUS
R
EGISTER
............................................................................................ 56
T
ABLE
19: R
X
DS3 FEAC R
EGISTER
................................................................................................................ 56
T
ABLE
20: R
X
DS3 FEAC I
NTERRUPT
E
NABLE
/S
TATUS
R
EGISTER
..................................................................... 57
T
ABLE
21: R
X
DS3 LAPD C
ONTROL
R
EGISTER
................................................................................................. 58
T
ABLE
22: R
X
DS3 LAPD S
TATUS
R
EGISTER
.................................................................................................... 59
T
ABLE
23: T
X
DS3 C
ONFIGURATION
R
EGISTER
.................................................................................................. 60
T
ABLE
24: T
X
DS3 M-B
IT
M
ASK
R
EGISTER
....................................................................................................... 61
T
ABLE
25: T
X
DS3 F-B
IT
M
ASK
1 R
EGISTER
...................................................................................................... 61
T
ABLE
26: T
X
D
S
3 F-B
IT
M
ASK
2 R
EGISTER
....................................................................................................... 62
T
ABLE
27: T
X
DS3 F-B
IT
M
ASK
3 R
EGISTER
...................................................................................................... 62
T
ABLE
28: T
X
DS3 F-B
IT
M
ASK
4 R
EGISTER
...................................................................................................... 63
T
ABLE
29: T
X
DS3 FEAC C
ONFIGURATION
AND
S
TATUS
R
EGISTER
................................................................... 63
T
ABLE
30: T
X
DS3 FEAC R
EGISTER
................................................................................................................. 64
T
ABLE
31: T
X
DS3 LAPD C
ONFIGURATION
R
EGISTER
....................................................................................... 64
T
ABLE
32: T
X
DS3 LAPD S
TATUS
/I
NTERRUPT
R
EGISTER
.................................................................................. 65
T
ABLE
33: PMON LCV E
VENT
C
OUNT
R
EGISTER
- MSB ................................................................................... 65
T
ABLE
34: PMON LCV E
VENT
C
OUNT
R
EGISTER
- LSB .................................................................................... 66
T
ABLE
35: PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- MSB .......................................................... 66
T
ABLE
36: PMON F
RAMING
B
IT
E
RROR
E
VENT
C
OUNT
R
EGISTER
- LSB ........................................................... 66
T
ABLE
37: PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- MSB ................................................................................ 66
T
ABLE
38: PMON P-B
IT
E
RROR
C
OUNT
R
EGISTER
- LSB ................................................................................. 67
T
ABLE
39: PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB ................................................................................ 67
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