參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 6/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
6
The Transmit DS3 Framer block will transmit FEAC
(Far-End-Alarm & Control) messages to the remote
terminal equipment via an “on-chip” FEAC Trans-
mitter.
The Transmit DS3 Framer block will also transmit
PMDL (Path Maintenance Data Link) Messages to
the remote terminal equipment via an “on-chip”
LAPD Transmitter.
THE MICROPROCESSOR INTERFACE SECTION
The Microprocessor Interface Section allows a user (or
a local “housekeeping” processor) to do the following:
To configure the UNI/Framer IC into a wide variety
of operating modes; by writing data into any one of
a large number of “read/write” registers.
To monitor many aspects of the UNI/Framer’s perfor-
mance by reading data from any one of a large num-
ber of “read/write” and “read-only” registers.
To run in a “polling” or “interrupt-driven” environment.
The UNI/Framer IC contains an extensive interrupt
structure consisting of a wide range of interrupt
enable and interrupt status registers.
To command the UNI/Framer IC to transmit OAM
cells, FEAC messages and/or LAPD Messages
frames, upon software command.
To read in and process received OAM cells, FEAC
messages and/or Path Maintenance Data Link
Messages from the UNI/Framer IC.
The Microprocessor Interface allows the user to
interface the XRT72L71 DS3 UNI/Framer to either
an Intel type or Motorola type processor. Addition-
ally, the Microprocessor Interface can be configured
to operate over an 8-bit or 16-bit data bus.
The Microprocessor Interface section includes a
“Loss of Clock Signal” protection feature that auto-
matically completes (or terminates) a “Read/Write”
operation, should a “Loss of Clock Signal” event
occur.
PERFORMANCE MONITOR SECTION
The Performance Monitor Section of the XRT72L71
DS3 UNI/Framer consists of a large number of “Re-
set-upon-Read” and “Read-Only” registers that con-
tains cumulative and “one-second” statistics that re-
flect the performance/health of the UNI/Framer chip/
system. These cumulative and “one-second” statis-
tics are kept on the following parameters.
Number of Line Code Violation events detected by
the Receive DS3 Framer
Number of Framing Bit (F- and M-bit) errors
detected by the Receive DS3 Framer
Number of P-bit Errors detected by the Receive
DS3 Framer
Number of CP-bit Errors detected by the Receive
DS3 Framer.
Number of FEBE Events detected by the Receive
DS3 Framer
Cumulative number of BIP-8 errors, detected by the
Receive PLCP Processor
Number of PLCP framing errors, detected by the
Receive PLCP Processor
Cumulative sum of the FEBE value, in the incoming
G1 bytes (within each PLCP frame), received by
the Receive PLCP Processor
Number of Single-bit HEC byte Errors detected
Number of Multi-bit HEC byte Errors detected
Number of Received Idle Cells
Number of Received Valid (User and OAM) cells
discarded
Number of Discarded Cells
Number of Transmitted Idle Cells
Number of Transmitted Valid Cells
TEST AND DIAGNOSTIC SECTION
The Test and Diagnostic Section allows the user to
perform a series of tests in order to verify proper func-
tionality of the UNI/Framer chip and/or the user’s sys-
tem. The “Test and Diagnostic” section provides the
UNI IC with the following capabilities.
Allows the UNI/Framer to operate in the Line, Cell,
and PLCP Loop-back Modes.
FOR ATM UNI APPLICATIONS
Contains an internal Test Cell Generator and an
internal Test Cell Receiver. The Test Cell Generator
will generate Test Cells with “user-defined” header
byte patterns. The Test Cell Generator will also fill
the payload portion of these test cells with bytes
from an on-chip PRBS generator.
The Test Cell Generator can generate test cells in
“One Shot” Mode (e.g., a burst of 1024 test cells) or in
“Continuous” Mode (e.g., a continuous stream of
test cells).
The Test Cell Receiver will identify and collect the
Test Cells for further analyses, based upon the
“user-defined” header byte patterns. Additionally,
the Test Cell Receiver will report the occurrence of
any errors by incrementing an on-chip register.
FOR CLEAR-CHANNEL FRAMING APPLICATIONS
Contains an internal PRBS pattern generator and
receiver. The PRBS pattern generator will generate
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