XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
16
28
LLOOP
O
Local Loop-back Output Pin (to the XRT7300 E3/DS3/STS-1 LIU IC):
This
output pin is intended to be connected to the LLOOP input pin of the XRT7300
LIU IC. This input pin, along with “RLOOP” (pin 26) permits the user to config-
ure the XRT7300 LIU IC to operate in either of the following three (3) loop-
back modes.
Analog Local Loop-Back Mode
Digital Local Loop-Back Mode
Remote Loop-Back Mode.
Writing a “1” to bit 1 of the “Line Interface Drive Register” (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause
the RLOOP output to toggle “Low”.
N
OTE
:
If the user is not using the XRT7300 DS3/E3/STS-1 LIU IC, then this
output pin can be used for other purposes.
29
Int
O
Interrupt Request Output:
This open-drain, active-”Low” output signal will be
asserted when the UNI/Framer is requesting interrupt service from the local
microprocessor. This output pin should typically be connected to the “Interrupt
Request” input of the local microprocessor.
30
RxLCD
O
Loss of Cell Delineation Indicator:
This active-"High" output pin will be
asserted whenever the Receive Cell Processor has experienced a “Loss of
Cell Delineation”. This pin will return “Low” once the Receive Cell Processor
has regained Cell Delineation.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
31
GND
***
Ground Pin Signal
32
CS
I
Chip Select Input:
This active-”Low” input signal selects the Microprocessor
Interface Section of the UNI/Framer and enables Read/Write operations
between the “l(fā)ocal” microprocessor and the UNI/Framer on-chip registers and
RAM locations.
33
RD_DS
I
Read Data Strobe (Intel Mode):
If the microprocessor interface is operating
in the Intel Mode, then this input will function as the RD (READ STROBE)
input signal from the local
μ
P
. Once this active-”Low” signal is asserted, then
the UNI/Framer will place the contents of the addressed registers (within the
UNI/Framer IC) on the Microprocessor Data Bus (D[15:0]). When this signal is
negated, the Data Bus will be tri-stated.
Data Strobe (Motorola Mode):
If the microprocessor interface is operating in
the Motorola mode, then this pin will function as the active-”Low” Data Strobe
signal.
34
RxGFC
O
Receive GFC Nibble Field Serial Output pin:
This pin, along with the RxG-
FCClk and the RxGFCMSB pins form the “Receive GFC Nibble-Field” serial
output port. This pin will serially output the contents of the GFC Nibble field of
each cell that is processed through the Receive Cell Processor. This data is
serially clocked out of this pin on the rising edge of the RxGFCClk signal. The
Most Significant Bit (MSB) of each GFC value is designated by a pulse at the
RxGFCMSB output pin.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
PIN DESCRIPTION (CONTINUED)
P
IN
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O
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YMBOL
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YPE
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ESCRIPTION