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參數(shù)資料
| 型號： | XRT72L71 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 18/104頁 |
| 文件大小： | 1156K |
| 代理商： | XRT72L71 |
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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
18
40
RxPOHFrame
O
Receive PLCP Frame Path Overhead (POH) Byte Serial Output Port—
Beginning of Frame Signal Pin:
This output pin, along with RxPOH, RxPO-
HClk, and RxPOHIns pins comprise the “Receive PLCP Frame POH Byte”
serial output port. This output pin provides framing information to external cir-
cuitry receiving and processing this POH (Path Overhead) data, by pulsing
“High” when the first bit of the Z6 byte is output via the RxPOH output pin. This
pin is “Low” at all other times during this PLCP POH framing cycle.
N
OTE
:
This output pin is only active if the XRT72L71 has been configued to
operate in the “ATM UNI” Mode.
41
42
43
44
45
46
A6
A5
A4
A3
A2
A1
I
Address Bus Input (Microprocessor Interface):
Please see description for A8, pin 37.
47
RxGFCMSB
O
Received GFC Nibble Field—MSB Indicator
: This output pin functions as a
part of the “Receive GFC-Nibble Field” Serial Output port; which also consists
of the RxGFC and RxGFCClk pins. This pin pulses “High” the instant that the
MSB (Most Significant Bit) of a GFC Nibble is being output on the RxGFC pin.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
48
A0
I
Address Bus Input (Microprocessor Interface)—LSB (Least Significant
Bit):
Please see description for A8, pin 37.
49
RxGFCClk
O
Received GFC Nibble Serial Output Port Clock Signal:
This output pin
functions as a part of the “Receive GFC Nibble-Field” Serial Output Port; also
consisting of the RxGFC and RxGFCMSB pins. This pin provides a clock
pulse which allows external circuitry to latch in the GFC Nibble-Data via the
RxGFC output pin.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
50
RxUClk
I
Receive UTOPIA Interface Clock Input:
The byte (or word) data, on the
Receive UTOPIA Data bus is updated on the rising edge of this signal. The
Receive UTOPIA Interface can be clocked at rates up to 50 MHz.
N
OTE
:
The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer’” Mode.
51
RxCellRxed
O
Receive Cell Processor—Cell Received Indicator:
This output pin pulses
“High” each time the Receive Cell Processor receives a new cell from the
Receive PLCP Processor or the Receive DS3 Framer.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
52
GND
***
Ground Pin Signal
53
RxUData15
O
Receive UTOPIA Data Bus Output (MSB):
This output pin, along with
RxUData14 through RxUData0 functions as the Receive UTOPIA Data Bus.
ATM cell data that has been received from the “Remote Terminal Equipment”
is output on the Receive UTOPIA Data Bus, where it can be read and pro-
cessed by the ATM Layer Processor.
N
OTE
:
This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
PIN DESCRIPTION (CONTINUED)
P
IN
N
O
.
S
YMBOL
T
YPE
D
ESCRIPTION
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