參數(shù)資料
型號： XRT72L71
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 76/104頁
文件大?。?/td> 1156K
代理商： XRT72L71
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
á
PRELIMINARY
76
T
ABLE
71:
R
X
PLCP I
NTERRUPT
S
TATUS
R
EGISTER
R
EGISTER
70 R
X
PLCP I
NTERRUPT
S
TATUS
R
EGISTER
H
EX
A
DDRESS
: 0
X
46
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-2
Unused
RO
0
1
POOF Interrupt Status
RUR
0
0: Indicates that the “Change in POOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in POOF Condition” interrupt has occurred
since the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L71is operating in both the
“ATM UNI” and the “PLCP” Modes.
0
PLOF Interrupt Status
RUR
0
0: Indicates that the “Change in PLOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in PLOF Condition” interrupt has occurred
since the last read of this register.
N
OTE
:
This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
T
ABLE
72:
F
UTURE
U
SE
R
EGISTER
71 F
UTURE
U
SE
H
EX
A
DDRESS
: 0
X
47
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
T
ABLE
73:
T
X
PLCP FA1 B
YTE
E
RROR
M
ASK
R
EGISTER
R
EGISTER
72 T
X
PLCP FA1 B
YTE
E
RROR
M
ASK
R
EGISTER
H
EX
A
DDRESS
: 0
X
48
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-0
FA1 Error Mask
R/W
0x00
The Transmit PLCP Processor block always XORs contents of this register
with the contents of the FA1 byte (within a PLCP frame). This “XORed” value
is then written back into the “FA1” byte field, within each “outbound” PLCP
Frame; prior to transmission. Setting any of these bit-fields to “1” introduces
error in that specific bit, within each “outbound” FA1 byte.
Register must be set to 0x00 for normal operation,
N
OTE
:
This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
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