參數(shù)資料
型號: W83977CTF-AW
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 69/161頁
文件大小: 592K
代理商: W83977CTF-AW
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-60 -
Revision A1
4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor and are the same as for the legacy UART
port. The table below illustrates the use of the baud generator with a frequency of 18,461 Mhz. The
output frequency of the baud generator is the baud rate multiplied by 16. In high-speed UART mode
(relies to Bank 0, Reg 6, Bit 1) the programmable baud generator directly uses 24 Mhz and the same
divisor. In high-speed mode, the baud rate can be as high as 1.5 M bps.
TABLE 3-5 BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50
2304
**
75
1536
**
110
1047
0.18%
134.5
857
0.099%
150
768
**
300
384
**
600
192
**
1200
96
**
1800
64
**
2000
58
0.53%
2400
48
**
3600
32
**
4800
24
**
7200
16
**
9600
12
**
19200
6
**
38400
3
**
57600
2
**
115200
1
**
1.5M
1
Note 1
0%
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit1 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
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