
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-7 -
Revision A1
1.1 Host Interface, continued
SYMBOL
PIN
I/O
FUNCTION
DACK0#
119
IN
tsu
DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,
default)
General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)
Alternate function from GP16: Watch dog timer output
KBC P15 I/O port. (CR2C bit 5_4 = 10)
GP16
(WDTO)
I/O
12t
P15
I/O
12t
OUT
12t
I/O
12t
DRQ0
GP17
(PLEDO)
121
DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)
General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)
Alternate function from GP17: Power LED output.
KBC P14 I/O port (CR2C bit 7_6 = 10)
System Control Interrupt (CR2C bit 7_6 = 11)
P14
SCI#
I/O
12t
OUT
12t
IN
ts
OUT
12t
IN
ts
OUT
12t
IN
ts
OUT
12t
IN
ts
DACK1#
122
DMA Channel 1 Acknowledge signal
DRQ1
123
DMA Channel 1 request signal
DACK2#
124
DMA Channel 2 Acknowledge signal
DRQ2
125
DMA Channel 2 request signal
DACK3#
126
DMA Channel 3 Acknowledge signal
DRQ3
127
DMA Channel 3 request signal
TC
128
Terminal Count. When active, this pin indicates termination of a
DMA transfer.
IRQ1
99
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
OUT
12t
Interrupt request 1
IRQ3
98
Interrupt request 3
IRQ4
97
Interrupt request 4
IRQ5
96
Interrupt request 5
IRQ6
95
Interrupt request 6
IRQ7
94
Interrupt request 7
IRQ9
92
Interrupt request 9
IRQ10
100
Interrupt request 10
IRQ11
101
Interrupt request 11
IRQ12
102
Interrupt request 12