參數(shù)資料
型號： W83977CTF-AW
英文描述： PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述： 周邊（多功能）控制器
文件頁數(shù)： 59/161頁
文件大小： 592K
代理商： W83977CTF-AW
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-50 -
Revision A1
1
2
3
4
5
6
7
0
RI falling edge (FERI)
DCD# toggling (TDCD)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
CTS# toggling (TCTS)
DSR# toggling (TDSR)
Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback
mode.
Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback
mode.
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high state after HSR was
read by the CPU.
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read.
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
1
2
3
4
5
6
7
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
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