
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-59 -
Revision A1
4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG), continued
Bit
Name
Read/Write
Description
5-4
LP_SL<1:0>
Read/Write
Low pass filter source selcetion.
LP_SL<1:0> = 00 Select raw IRRX signal.
LP_SL<1:0> = 01 Select R.B.P. signal
LP_SL<1:0> = 10 Select D.B.P. signal.
LP_SL<1:0> = 11 Reserved.
Receiver Demodulation Source Selection.
RXDMSL<1:0> = 00 select B.P. and L.P. filter.
RXDMSL<1:0> = 01 select B.P. but not L.P.
RXDMSL<1:0> = 10 Reserved.
RXDMSL<1:0> = 11 do not pass demodulation.
Baud Rate Pre-divisor. Set to 0, the baud rate
generator input clock is set to 1.8432M Hz which is set
to pre-divisor into 13. When set to 0, the pre-divisor is
set to 1, that is, the input clock of baud rate generator is
set to 24M Hz.
Receiving Signal Invert. Write to 1, Invert the receiving
signal.
3-2
RXDMSL<1:0>
Read/Write
1
PRE_DIV
Read/Write
0
RXINV
Read/Write
4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7
RXACT
Read/Write
Receive Active. Set to 1 whenever a pulse or pulse-
train is detected by the receiver. If a 1 is written into the
bit position, the bit is cleared and the receiver is de-
actived. When this bit is set, the receiver samples the
IR input continuously at the programmed baud rate and
transfers the data to the receiver FIFO.
6
RX_PD
Read Only
Set to 1 whenever a pulse or pulse-train (modulated
pulse) is detected by the receiver. Can be used by the
sofware to detect idle condition. Cleared Upon Read.
5
Reserved
-
-
4-0
FOLVAL
Read Only
FIFO Level Value. Indicates how many bytes there are
in the current received FIFO. Can read these bits then
get the FIFO level value and successively read RBR by
the prior value.