
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-56 -
Revision A1
4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR)
(BANK0~3)
Power on default <7:0> = 00000000 binary
Bit
Name
Read/Write
Description
7-6
BNK_SEL<1:0>
Read/Write
Bank Select Register. These two bits share the same
address so that
Bank Select Register (BSR)
can be
programmed to desired Bank in any Bank.
BNK_SEL<1:0> = 00 Select Bank 0.
BNK_SEL<1:0> = 01 Select Bank 1.
BNK_SEL<1:0> = Reserved.
BNK_SEL<1:0> = Reserved.
5-4
RXFTL1/0
Read/Write
Receiver FIFO Threshold Level. It sets the RXTH_I to
become 1 when the Receiver FIFO Threshold Level is
equal or larger than the defined value shown as follows.
RXFTL<1:0> = 00 -- 1 byte
RXFTL<1:0> = 01 -- 4 bytes
RXFTL<1:0> = 10 -- 8 bytes
RXFTL<1:0> = 11 -- 14 bytes
3
TMR_TST
Read/Write
Timer Test. Write to 1, then reading the TMRL/TMRH
will return the programmed values of TMRL/TMRH, that
is, it does not return down count counter value. This bit
is for test timer register.
2
EN_TMR
Read/Write
Enable timer. Write to 1, enable the timer
1
RXF_RST
Read/Write
Setting this bit to a logical 1 resets the RX FIFO
counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
0
TMR_CLK
Read/Write
Timer input clock.
TMR_CLK = 0, input clock set to 1K Hz.
TMR_CLK = 1, input clock set to 24M Hz. This clock is
tested by Winbond. Do not publish.