
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-58 -
Revision A1
4.2.6 Bank0.Reg5 - UART Line Status Register (USR)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7-3
Reserved
-
-
2
RX_TO
Read/Write
Set to 1 when receiver FIFO
or
frame status FIFO
occurs time-out. Read this bit to clear.
1
OV_ERR
Read/Write
Received FIFO overrun. Read to clear.
0
RDR
Read/Write
This bit is set to a logical 1 to indicate received data are
ready to be read by the CPU in the RBR or FIFO. After
no data are left in the RBR or FIFO, the bit will be reset
to a logical 0.
4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7-6
SMPSEL<1:0>
Read/Write
Sampling Mode Select. Select internal decoder
methodology from the internal filter. Selected decoder
mode will determine the receive data format. The
sampling mode is shown bellow:
SMPSEL<1:0> = 00 T-Period Sample Mode.
SMPSEL<1:0> = 01 Over-Sampling Mode.
SMPSEL<1:0> = 10 Over-Sampling with re-sync.
SMPSEL<1:0> = 11 FIFO Test Mode.
The T-period code format is defined as follows.
(Number of bits) - 1
B7
B6
B5
B4
B2
B1 B0
B3
Bit value
The Bit value is set to 0, when the low signal will be
received. The Bit value is set to 1, when the high signal
will be received. The opposite results will be generated
when the bit RXINV (Bank0.Reg6.Bit0) is set to 1.