
46
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Suspend and Resume Behavior
(continued)
Special Suspend Considerations for Bus-
Powered Devices
(continued)
I
D[7:0], SOFN*: Bidirectional pins, forced to input
mode while suspended (assuming
SSR.SUSPPO = 1). Their value will be determined
by external logic, and must be a logic 0 or 1 to avoid
current draw in the USS-820D.
I
IRQN, USBR, DSA: 3-statable outputs, forced to
3-state during suspend (assuming
SSR.SUSPPO = 1, MCSR.BDFEAT = 0). Their value
will be determined by external logic, and is a don’t
care for the USS-820D.
I
DPLS, DMNS: Bidirectional pins, in input mode dur-
ing suspend, driven by USB. Since they are statically
driven to 1 and 0, respectively, there is no current
draw in the USS-820D.
I
RWUPN: Input-only pin, driven to 1 by (powered)
external logic during suspend, unless/until a remote
wake-up is signalled.
I
SUSPN: Output-only pin, driven to 0 by USS-820D to
indicate suspend.
I
XTAL1: Input connection to internal oscillator. If a
crystal is used as a clock source, there are no spe-
cial considerations for this pin. If an external oscilla-
tor is used as a clock source, this input must be
driven to a stable 1 by external logic.
I
RESET: Driven to 0 during suspend by external logic.
I
DPPU: 3-statable output, drives a logic 1 during sus-
pend (assuming MCSR.DPEN = 1). This is required
in case the pin is used to power the external DPLS
pull-up resistor, which must remain powered during
suspend.
Depending on the device design, the USS-820D
register interface signals (RDN, WRN, IOCSN) could
have unknown values immediately after a suspend
because external components have been powered off.
In this case, firmware must configure the USS-820D to
enable the locking mechanism by setting the
MCSR.SUSPLOE register bit. This mechanism
protects the internal registers from being corrupted in
this situation. Its behavior is documented in
Special
Action Required by USS-820/USS-825 After Suspend
Application Note (AP97-058CMPR-04).
* SOFN is an output-only pin during normal operation. In certain chip
test modes, this pin functions as an input.