參數(shù)資料
型號(hào)： USS-820D
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁(yè)數(shù)： 39/58頁(yè)
文件大?。?/td> 868K
代理商： USS-820D
Agere Systems Inc.
39
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 36. Miscellaneous Control/Status Register (MCSR)—Address: 1CH; Default:
0000 0000B (44-Pin MQFP—USS-820D)
0001 0000B (48-Pin TQFP—USS-820TD)
This register contains miscellaneous control and status bits.
Bit 7
RWUPR
R
Bit 6
INIT
R
Bit 5
SUSPS
R
Bit 4
PKGID
R
Bit 3
FEAT
R/W
Bit 2
BDFEAT
R/W
Bit 1
Bit 0
DPEN
R/W
SUSPLOE
R/W
Bit
7
Symbol
RWUPR
Function/Description
Remote Wake-Up Remember.
This bit is only available if MCSR.FEAT = 1; otherwise, it
always reads 0. Updated by hardware on each wake-up from a suspended state. This bit
is set to 1 if the wake-up was caused by a remote wake-up event (RWUPN pin asserted).
Otherwise, it is reset to 0 (on a global resume or USB reset). If RWUPN is asserted
simultaneously with a global wake-up, the bit is reset to 0 (global wake-up wins). When
set, this bit indicates that resume signaling will be transmitted upstream.
Device Initialized.
This bit will read 0 until internal clocks are turned on after a hardware
reset. This bit is not affected by software reset. This bit can be used by firmware to deter-
mine when the device is operational after a hardware reset.
Suspend Status.
Indicates the current suspended status of the device. This bit will be
set when the device goes suspended and will remain set until internal clocks are turned
back on at the end of a resume sequence.
Package Identification.
Indicates the package type. This bit will read 0 for the 44-pin
MQFP package (USS-820D) and 1 for the 48-pin TQFP package (USS-820TD). This
value is established at the end of a hardware reset sequence.
Feature Enable.
When set, this bit enables various features introduced in revision C of
the USS-820C. This bit controls those features which do not impact existing circuit
boards using the USS-820 revision B (i.e., those features not enabled by
MCSR.BDFEAT). These features are explained in detail in the Appendix C of the data
sheet. When reset to 0 (along with MCSR.BDFEAT, TXSTAT.TXDSAM and
TXSTAT.TXNAKE), the device will behave like revision B.
Board Feature Enable.
When set, this bit enables various features introduced in revi-
sion C of the USS-820C. This bit controls those features which could be incompatible
with existing circuit boards using the USS-820 revision B. These features are explained
in detail in Appendix C of the data sheet. When reset to 0 (along with MCSR.FEAT,
TXSTAT.TXDSAM and TXSTAT.TXNAKE), the device will behave like revision B.
Suspend Lock Out Enable.
Enables the device locking mechanism, which will then
engage on every device resume. The correct value of this bit must be established before
firmware suspends the device.
DPLS Pull-Up Enable.
Controls the DPPU output pin, which may be used to power the
external DPLS pull-up resistor. This can be used by firmware to make the device appear
disconnected from the host without a physical disconnect. When DPEN = 1, the DPPU
output pin is driven high. When DPEN = 0, the DPPU output pin is 3-stated.
6
INIT
5
SUSPS
4
PKGID
3
FEAT
2
BDFEAT
1
SUSPLOE
0
DPEN
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