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參數(shù)資料
| 型號： | USS-820D |
| 英文描述： | USS-820D USB Device Controller |
| 中文描述： | 號- 820D USB設(shè)備控制器 |
| 文件頁數(shù)： | 33/58頁 |
| 文件大小： | 868K |
| 代理商： | USS-820D |
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Agere Systems Inc.
33
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 29. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B
These flags indicate the status of the data packets in the receive FIFO specified by EPINDEX. This register is
endpoint indexed.
Bit 7
RXFIF1
Bit 6
RXFIF0
Bit 5
—
—
Bit 4
Bit 3
RXEMP
Bit 2
RXFULL
Bit 1
RXURF
Bit 0
RXOVF
RXFLUSH
R
R
R
R/W
Bit
7:6
Symbol
RXFIF[1:0]
Function/Description
Receive FIFO Index Flags (Read Only).
These read-only flags indicate which data
packets are present in the receive FIFO (see below).
Data Sets Present
RXFIF[1:0]
ds1
ds0
00
No
No
01
No
Yes
10
Yes
No
11
Yes
Yes
Status
Empty
1 set
1 set
2 sets
The RXFIF bits are updated after each write to RXCNT to reflect the addition of a data
packet. Likewise, the RXFIF bits are cleared in sequence after each setting of the
RXFFRC bit. The next-state table for RXFIF bits is shown below for operation in dual-
packet mode.
RXFIF[1:0]
Operation
Next RXFIF[1:0]
00
Advance Write Marker
01
Advance Write Marker
10
Advance Write Marker
11
Advance Write Marker
Not Possible—Device
will NACK any OUT.
01
11
11
11
00
01
11
10
Set RXFFRC
Set RXFFRC
Set RXFFRC
Set RXFFRC
00
00
10/01
00
00
Reverse Write Pointer
Unchanged
When the receive FIFO is programmed to operate in single-packet mode (RXSPM set in
EPCON), valid RXFIF states are 00 and 01 only.
In isochronous mode, RXOVF, RXURF, and RXFIF are handled using the following rule:
firmware events cause status change immediately, while USB events cause status
change only at SOF. RXFIF is incremented by the USB and decremented by firmware.
Therefore, setting RXFFRC decrements RFIF immediately. However, a successful USB
transaction within a frame increments RXFIF only at SOF.
If MCSR.FEAT = 1:
An old data set is flushed from an isochronous FIFO if it is not read out by firmware
during the intended frame (see RXFLG.RXFLUSH description). This flush occurs at
SOF, sets RXFLG.RXFLUSH, and causes RXFIF to decrement without firmware
intervention.
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