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參數(shù)資料
| 型號： | USS-820D |
| 英文描述： | USS-820D USB Device Controller |
| 中文描述： | 號- 820D USB設備控制器 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 868K |
| 代理商： | USS-820D |
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Agere Systems Inc.
23
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 19. Endpoint Transmit Status Register (TXSTAT)—Address: 0CH; Default: 0000 0000B
(continued)
* For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such
as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal
USB traffic, as documented in the USB specification, Section 8.6.
Only writable if TXNAKE = 1.
Bit
3
Symbol
TXSOVW
Function/Description
Transmit Data Sequence Overwrite Bit.
* Writing a 1 to this bit allows the value of
the TXSEQ bit to be overwritten. Writing a 0 to this bit has no effect on TXSEQ. This
bit always returns 0 when read.
Transmit Void.
Behavior when TXNAKE = 0:
This bit is read only if TXNAKE = 0. Indicates a void condition has occurred in
response to a valid IN token. Transmit void is closely associated with the NACK/
STALL handshake returned by the function after a valid IN token. This void condi-
tion occurs when the endpoint output is disabled (TXOE = 0) or stalled (TXSTL =
1), the corresponding receive FIFO contains a setup packet (RXSETUP = 1), the
FIFO contains no valid data sets (TXFIF = 00), or there is an existing FIFO error
(TXURF = 1 or TXOVF = 1).
2
TXVOID
This bit is used to check any NACK/STALL handshake returned by the function.
This bit does not affect the FTXDx, TXERR, or TXACK bits. This bit is updated by
hardware at the end of a nonisochronous transaction in response to a valid IN
token. For isochronous transactions, this bit is not updated until the next SOF. This
bit is not updated at SOF if TXFLUSH is performed.
Behavior when TXNAKE = 1:
When TXNAKE = 1, this bit becomes writable by firmware. The meaning of the bit
is also changed, to indicate only that a NAK was sent to the host in response to an
IN when TXFIF = 00. Hardware setting of this bit always takes priority over firm-
ware writes. Hardware setting of this bit also causes the corresponding SBI/SBI1
bit to set, possibly causing an interrupt. That setting will persist until TXVOID is
cleared by firmware.
Transmit Error (Read Only).
Indicates an error condition has occurred with the
transmission. Complete or partial data has been transmitted. The error can be one of
the following:
1. Data transmitted successfully but no handshake received.
2. Transmit FIFO goes into underrun condition while transmitting.
1
TXERR
These conditions also cause the corresponding transmit done bit, FTXDx in SBI or
SBI1, to be set. For nonisochronous transactions, TXERR is updated by hardware
along with the TXACK bit at the end of data transmission. TEXERR and TXACK are
updated at the same time—one bit is set to 1, and the other is reset to 0. For isochro-
nous transactions, TXERR is not updated until the next SOF. This bit is not updated at
SOF if TXFLUSH is performed.
Transmit Acknowledge (Read Only).
Indicates data transmission completed and
acknowledged successfully. This condition also causes the corresponding transmit
done bit, FTXDx in SBI or SBI1, to be set. For nonisochronous transactions, TXACK
is updated by hardware along with the TXERR bit at the end of data transmission.
TEXERR and TXACK are updated at the same time—one bit is set to 1, and the other
is reset to 0. For isochronous transactions, TXACK is not updated until the next SOF.
This bit is not updated at SOF if TXFLUSH is performed.
0
TXACK
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