參數(shù)資料
型號(hào)： USS-820D
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁(yè)數(shù)： 21/58頁(yè)
文件大?。?/td> 868K
代理商： USS-820D
Agere Systems Inc.
21
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 18. Endpoint Control Register (EPCON)—Address: 0BH; Default: Endpoint 0 = 0011 0101B;
Others = 0001 0000B
This SFR configures the operation of the endpoint specified by EPINDEX. This register is endpoint indexed.
* S = shared bit. P = PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section.
Bit 7
RXSTL
R/W (S*)
Bit 6
TXSTL
Bit 5
CTLEP
Bit 4
RXSPM
Bit 3
RXIE
R/W(P*)
Bit 2
RXEPEN
Bit 1
TXOE
Bit 0
TXEPEN
Bit
7
Symbol
RXSTL
Function/Description
Stall Receive Endpoint
. When set, this bit stalls the receive endpoint. Firmware
must clear this bit only after the host has intervened through commands sent down
endpoint 0. When this bit is set and RXSETUP is clear, the receive endpoint responds
with a STALL handshake to a valid OUT token. When this bit is set and RXSETUP is
set, the receive endpoint will NACK. This bit does not affect the reception of SETUP
tokens by a control endpoint. This bit is set by the hardware if the data phase of the
status stage of a control transfer does not use the correct data PID (DATA1) or has
more than 0 data bytes.
Stall Transmit Endpoint
. When set, this bit stalls the transmit endpoint. Firmware
must clear this bit only after the host has intervened through commands sent down
endpoint 0. When this bit is set and RXSETUP is clear, the transmit endpoint
responds with a STALL handshake to a valid IN token. When this bit is set and
RXSETUP is set, the receive endpoint will NACK.
Control Endpoint
. When set, this bit configures the endpoint as a control endpoint.
Only control endpoints are capable of receiving SETUP tokens.
Receive Single-Packet Mode
. When set, this bit configures the receive endpoint for
single data packet operation. When enabled, only a single data packet is allowed to
reside in the receive FIFO.
6
TXSTL
5
CTLEP
4
RXSPM
Note:
For control endpoints (CTLEP = 1), this bit should be set for single-packet
mode operation as the recommended firmware model. However, it is possible
to have a control endpoint configured in dual-packet mode as long as the firm-
ware handles the endpoint correctly.
Receive Input Enable
. When set, this bit enables data from the USB to be written
into the receive FIFO. If cleared, the endpoint responds to an OUT token by ignoring
the data and returning a NACK handshake to the host (unless RXSTL is set, in which
case a STALL is returned). This bit does not affect a valid SETUP token.
Receive Endpoint Enable
. When set, this bit enables the receive endpoint. When
disabled, the endpoint does not respond to a valid OUT or SETUP token. This bit is
hardware read only and has the highest priority among RXIE and RXSTL.
3
RXIE
2
RXEPEN
Note:
Endpoint 0 is enabled for reception upon reset.
Transmit Output Enable
. When set, this bit enables the data in TXDAT to be trans-
mitted. If cleared, the endpoint returns a NACK handshake to a valid IN token if the
TXSTL bit is not set.
Transmit Endpoint Enable
. When set, this bit enables the transmit endpoint. When
disabled, the endpoint does not respond to a valid IN token. This bit is hardware read
only.
1
TXOE
0
TXEPEN
Note:
Endpoint 0 is enabled for transmission upon reset.
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