參數(shù)資料
型號(hào)： USS-820D
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁(yè)數(shù)： 36/58頁(yè)
文件大?。?/td> 868K
代理商： USS-820D
36
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 30. System Control Register (SCR)—Address: 11H; Default: 0000 0000B
This register controls the FIFO mode, IRQ mask, and IRQ mode selection.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQPOL
RWUPE
IE_SUSP
IE_RESET
R/W
SRESET
IRQLVL
T_IRQ
—
—
Bit
Symbol
Function/Description
7
IRQPOL
IRQ Polarity.
Determines the polarity of the IRQN output. When asserted, the IRQN output is
active-high (default is active-low). Firmware must be careful to ensure that setting this bit does
not cause a false interrupt to be detected and processed.
Enable Remote Wake-Up Feature.
When set, remote wake-up is enabled.
Enable Suspend Interrupt.
When set, the SUSPEND interrupt is enabled.
IE_RESET
Enable Reset Interrupt.
When set, the RESET interrupt is enabled.
SRESET
Software Reset.
Setting this bit to 1 in software places the USS-820D in the RESET state. This
is equivalent to asserting the hardware RESET pin, except that this feature is not available if
the device is suspended. Setting this bit back to 0 leaves the USS-820D in an unconfigured
state that follows a hardware reset.
If MCSR.FEAT = 1, SSR.SUPPO = 0 and MCSR.SUSPLOE = 0:
This bit may also be set to 1 while the device is suspended. The effect of this write is to
wake up the device as if a remote wake-up had been performed, with the following excep-
tions: 1) Resume signaling is not transmitted to the host, 2) The feature is enabled regard-
less of the SCR.RWUPE setting, and 3) The MCSR.RWUPR register bit does not set. The
actual setting of the SCR.SRESET register bit does not occur until the device is resumed
and internal clocks are enabled, but the wake-up is initiated immediately. Once the wake-up
is complete, the SRESET bit sets, and the behavior is the same as if SRESET had been set
while the device was awake. Since the host will still expect the device to be suspended, this
feature should not be used with bus-powered devices, since the device will exceed the
suspend power requirement.
IRQLVL
Interrupt Mode.
Level mode interrupt is selected when this bit is cleared. Pulse mode interrupt
is selected when this bit is set. In pulse mode, IRQ signal is driven (high or low, depending on
the IRQPOL setting) by USS-820D for two t
CLK
periods.
T_IRQ
Global Interrupt Enable.
When this bit is set, it enables hardware interrupt to be generated on
IRQ pin when any of TX/RX bits, ASOF bit, RESET bit, or SUSPEND bit is set.
—
Reserved.
Write 0 to this bit. Reads always return 0.
6
5
4
3
RWUPE
IE_SUSP
2
1
0
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