參數(shù)資料
型號: USS-820D
英文描述: USS-820D USB Device Controller
中文描述: 號- 820D USB設備控制器
文件頁數(shù): 38/58頁
文件大小: 868K
代理商: USS-820D
38
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 33. Suspend Power-Off Locking Register (LOCK)—Address: 19H; Default: 0000 0001B
This register contains the control and status which enables the USS-820D locking mechanism. This feature
protects the internal register set from being corrupted during and immediately after a suspend where the external
controller is powered off. The feature is enabled by the SUSPLOE bit, and its proper usage is documented in the
Special Action Required by USS-820/USS-825 After Suspend
Application Note (AP97-058CMPR-04).
Table 34. Pend Hardware Status Update Register (PEND)—Address: 1AH; Default: 0000 0000B
This register contains the PEND bit.
Table 35. Scratch Firmware Information Register (SCRATCH)—Address: 1BH; Default: 0000 0000B
This register contains a 7-bit scratch field that can be used by firmware to save and restore information. One
possible use would be to save the device’s USB state (e.g., DEFAULT, ADDRESSED) during suspend power off.
The register also contains the resume interrupt enable bit.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UNLOCKED
R/W
Bit
7:1
0
Symbol
UNLOCKED
Function/Description
Reserved.
Locking Control/Status.
Use of this bit is described in the
Special Action Required by
USS-820/USS-825 After Suspend
Application Note (AP97-058CMPR-04).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEND
R/W
Bit
7:1
0
Symbol
PEND
Function/Description
Reserved.
Pend.
When set, this bit modifies the behavior of other shared register bits. See the
Special Firmware Action for Shared Register Bits section of this document for a detailed
explanation.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SCRATCH
R/W
Bit 2
Bit 1
Bit 0
IE_RESUME
R/W
Bit
7
6:0
Symbol
IE_RESUME
SCRATCH
Function/Description
Enable Resume Interrupt.
When set, the RESUME interrupt is enabled.
Scratch Information.
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