Agere Systems Inc.
27
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 24. USB Transmit FIFO Control Register (TXCON)—Address: 03H; Default: 0000 0100B
This register controls the transmit FIFO specified by EPINDEX. This register is endpoint indexed.
* Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes.
ATM mode is recommended for normal operation. ADVRM and REVRP, which control the read marker and read pointer when ATM = 0, are
used for test purposes.
Bit 7
TXCLR
Bit 6
FFSZ1
R/W
Bit 5
FFSZ0
Bit 4
—
—
Bit 3
TXISO
Bit 2
ATM
Bit 1
ADVRM
Bit 0
REVRP
R/W
Bit
7
Symbol
TXCLR
Function/Description
Transmit FIFO Clear.
Setting this bit flushes the transmit FIFO, resets all the read/write
pointers and markers, resets the TXCNTH and TXCNTL registers, resets the TXFLUSH,
TXVOID, TXERR, and TXACK bits of the TXSTAT register, sets the TXEMP bit in TXFLG,
and clears all other bits in TXFLG. Hardware clears this bit after the flush. Setting this bit
does not affect the TXSEQ bit in the TXSTAT register. This bit should only be set when the
endpoint is known to be inactive or there is a FIFO error present.
FIFO Size.
These bits select the size of the transmit FIFO.
6:5
FFSZ[1:0]
FFSZ[1:0]
00
01
10
11
Reserved.
Write 0 to this bit. Reads always return 0.
Transmit Isochronous Data.
Firmware sets this bit to indicate that the transmit FIFO
contains isochronous data. The SIE uses this bit to determine if a handshake is required at
the end of a transmission.
Automatic Transmit Management.
Setting this bit (the default value) causes the read
pointer and read marker to be adjusted automatically as indicated:
Nonisochronous Size
16
64
8*
32*
Isochronous Size
64
256
512
1024
4
3
—
TXISO
2
ATM
Status
ACK
NACK
Read Pointer
Unchanged
Reversed (2)
Read Marker
Advanced (1)
Unchanged
1. To origin of next data set.
2. To origin of the data set last read.
This bit should always be set, except for test purposes. Setting this bit disables ADVRM
and REVRP. This bit can be set and cleared by firmware. Hardware neither clears nor sets
this bit. This bit must always be set for isochronous endpoints (TXISO = 1).
Advance Read Marker Control (Non-ATM Mode Only).
Setting this bit prepares for the
next packet transmission by advancing the read marker to the origin of the next data
packet (the position of the read pointer). Hardware clears this bit after the read marker is
advanced. This bit is effective only when the REVRP, ATM, and TXCLR bits are clear.
Reverse Read Pointer (Non-ATM Mode Only).
In the case of a bad transmission, the
same data stack may need to be available for retransmit. Setting this bit reverses the read
pointer to point to the origin of the last data set (the position of the read marker) so that the
SIE can reread the last set for retransmission. Hardware clears this bit after the read
pointer is reversed. This bit is effective only when the ADVRM, ATM, and TXCLR bits are
all clear.
1
ADVRM
0
REVRP