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參數(shù)資料
| 型號： | USS-820D |
| 英文描述： | USS-820D USB Device Controller |
| 中文描述： | 號- 820D USB設(shè)備控制器 |
| 文件頁數(shù)： | 29/58頁 |
| 文件大?。?/td> | 868K |
| 代理商： | USS-820D |
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Agere Systems Inc.
29
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 25. Transmit FIFO Flag Register (TXFLG)—Address: 04H; Default: 0000 1000B
(continued)
Bit
7:6
Symbol
TXFIF[1:0]
Function/Description
Transmit FIFO Index Flags (Read Only)
(continued).
If MCSR.FEAT = 1:
data set. Prior to that SOF, the device will return a zero-length data set in response to
an IN (unless there is another, older data set present from the prior frame). This ensures
that a given data set may only be sent during the subsequent frame, as required by the
USB specification. This behavior also allows firmware to occasionally be late in writing a
data set (write complete after SOF), without losing frame/data synchronization with the
host. The late data set write will cause a zero-length data set to be sent to the host
during the intended frame. The late set will be flushed at the end of the next frame,
assuming firmware also writes the correct data set during that frame (see
TXSTAT.TXFLUSH description). Firmware must not be late on consecutive frames (this
will cause a loss of frame/data synchronization with the host), data sets may be sent
during the wrong frame.
Note:
Firmware can enforce single-packet mode by only writing a new data set to the
transmit FIFO if there are currently no data sets present in the FIFO (TXFIF = 00).
To simplify firmware development, configure control endpoints in single-packet
mode.
Reserved.
Write 0s to these bits. Reads always return 0s.
Transmit FIFO Empty Flag (Read Only).
Hardware sets this bit when firmware has not
yet written any data bytes to the current FIFO data set being written. Hardware clears this
bit when the empty condition no longer exists.
This bit always tracks the current transmit FIFO status regardless of isochronous or
nonisochronous mode.
Transmit FIFO Full Flag (Read Only).
Hardware sets this bit when the number of bytes
that firmware writes to the current transmit FIFO data set equals the FIFO size. Hardware
clears this bit when the full condition no longer exists.
This bit always tracks the current transmit FIFO status regardless of isochronous or
nonisochronous mode. Check this bit to avoid causing a TXOVF condition.
Transmit FIFO Underrun Flag (Read, Clear Only).
Hardware sets this flag when a read
is attempted from an empty transmit FIFO. (This is caused when the value written to
TXCNT is greater than the number of bytes written to TXDAT.) This bit must be cleared by
firmware through TXCLR. When this flag is set, the FIFO is in an unknown state; there-
fore, it is recommended that the FIFO is reset in the error management routine using the
TXCLR bit in TXCON.
When the transmit FIFO underruns, the read pointer does not advance; it remains locked
in the empty position.
When this bit is set, all transmissions are NACKed.
In isochronous mode, TXOVF, TXURF, and TXFIF are handled using the following rule:
firmware events cause status change immediately, while USB events cause status change
only at SOF. Since underrun can only be caused by USB, TXURF is updated at the next
SOF regardless of where the underrun occurs in the frame.
5:4
3
—
TXEMP
2
TXFULL
1
TXURF
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