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參數(shù)資料
| 型號： | USS-344 |
| 英文描述： | USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| 中文描述： | 號，344 QuadraBus四主機的PCI到USB主機控制器OpenHCL |
| 文件頁數(shù)： | 51/54頁 |
| 文件大?。?/td> | 850K |
| 代理商： | USS-344 |
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Agere Systems Inc.
51
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USS-344
QuadraBus
Electrical Characteristics
(continued)
Table 141
.
5 V and 3.3 V PCI Timing Parameters
1. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1.
2. For parts compliant to the 5 V signaling environment:
Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load. Actual test capacitance
may vary, but results should be correlated to these specifications. Note that faster buffers may exhibit some ring back when attached to a
50 pF lump load, which should be of no consequence as long as the output buffers are in full compliance with slew rate and V/I curve spec-
ifications.
For parts compliant to the 3.3 V signaling environment:
Minimum times are evaluated with same load used for slew rate measurement (see PCI Specification, Rev. 2.1s); maximum times are eval-
uated with the following load circuits, for high-going and low-going edges, respectively.
3. REQN and GNTN are point-to-point signals and have different output valid delay and input setup times than bused signals. GNTN has a
setup time of 10 ns; REQN has a setup time of 12 ns. All other signals are bused.
4. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1.
5. RSTN is asserted and deasserted asynchronously with respect to CLK.
6. All output drivers must be asynchronously floated when RSTN is active.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the compo-
nent pin is less than or equal to the leakage current specification.
Symbol
t
VAL
t
VAL(ptp)
t
ON
t
OFF
t
SU
t
SU(ptp)
t
H
t
RST
t
RST-CLK
t
RST-OFF
t
RRSU
t
RRH
Parameter
Min
2
2
2
—
7
10, 12
0
1
100
—
10
×
t
CYC
0
Max
11
12
—
28
—
—
—
—
—
40
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK to Signal Valid Delay—Bused Signals
1, 2, 3
CLK to Signal Valid Delay—Point to Point
1, 2, 3
Float to Active Delay
1, 7
Active to Float Delay
1, 7
Input Setup Time to CLK—Bused Signals
3, 4
Input Setup Time to CLK—Point to Point
3, 4
Input Hold Time from CLK
4
Reset Active Time After Power Stable
5
Reset Active Time After CLK Stable
5
Reset Active to Output Float Delay
5, 6, 7
REQN to RSTN Setup Time
RSTN to REQN Hold Time
OUTPUT
BUFFER
1/2 IN. MAX.
PIN
25
10 pF
T
VAL
(MAX) RISING EDGE
1/2 IN. MAX.
25
10 pF
T
VAL
(MAX) FALLING EDGE
V
CC
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| USS-344QUADRABUS | 制造商:AGERE 制造商全稱:AGERE 功能描述:Four-Host PCI-to-USB OpenHCI Host Controller |
| USS344S-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| USS-4(1m) | 制造商:Ubon 功能描述:1m 1 to 0.4mm D Bulk |
| USS4350 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
| USS4350G-AA3-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
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