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參數(shù)資料
| 型號： | USS-344 |
| 英文描述： | USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| 中文描述： | 號，344 QuadraBus四主機(jī)的PCI到USB主機(jī)控制器OpenHCL |
| 文件頁數(shù)： | 37/54頁 |
| 文件大小： | 850K |
| 代理商： | USS-344 |
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Advance Data Sheet, Rev. 9
June 2001
Agere Systems Inc.
37
Four-Host PCI-to-USB OpenHCI Host Con-
USS-344
QuadraBus
Legacy Support Registers
(continued)
HceControl Register
Table 126. HceControl Register (100h)
Bit
0
Field
Reset
0b
R/W
R/W
Description
EmulationEnable
When set to 1, the HC is enabled for legacy emulation. The
HC decodes accesses to I/O registers 60h and 64h and gen-
erates IRQ1 and/or IRQ12 when appropriate. Additionally,
the HC generates an emulation interrupt at appropriate times
to invoke the emulation software.
This bit is a static decode of the emulation interrupt condi-
tion.
When set, an emulation interrupt is generated when the Out-
putFull bit of the HceStatus register is set to 0.
When set, the HC generates IRQ1 or IRQ12 as long as the
OutputFull bit in HceStatus is set to 1. If the AuxOutputFull
bit of HceStatus is 0, then IRQ1 is generated; if it is 1, then
an IRQ12 is generated.
When set to 1, IRQ1 and IRQ12 from the keyboard controller
causes an emulation interrupt. The function controlled by this
bit is independent of the setting of the EmulationEnable bit in
this register.
Set by HC when a data value of D1h is written to I/O port
64h. Cleared by HC on write to I/O port 64h of any value
other than D1h.
Indicates that a positive transition on IRQ1 from keyboard
controller has occurred. SW may write a 1 to this bit to clear
it (set it to 0). SW write of a 0 to this bit has no effect.
Indicates that a positive transition on IRQ12 from keyboard
controller has occurred. SW may write a 1 to this bit to clear
it (set it to 0). SW write of a 0 to this bit has no effect.
Indicates current state of gate A20 on keyboard controller.
Used to compare against value written to 60h when
GateA20Sequence is active.
Must read as 0s.
1
EmulationInterrupt
—
R
2
CharacterPending
0b
R/W
3
IRQEn
0b
R/W
4
ExternalIRQEn
0b
R/W
5
GateA20Sequence
0b
R/W
6
IRQ1Active
0b
R/W
7
IRQ12Active
0b
R/W
8
A20State
0b
R/W
31:9
Reserved
—
—
Connection Instructions
Figure 6 shows a typical connection of the USS-344 to
provide four USB ports and full legacy support to a
PCI-based system. For each of the following sections,
refer to Figure 6 for guidance.
PCI Connection Instructions
The USS-344 interfaces directly with any 32-bit,
33 MHz PCI bus simply by connecting all PCI related
signals directly to the signals on the host motherboard
or card edge of an expansion card. The PCI signaling
level for all PCI signals of the USS-344 is selected by
connecting the VIO signal to the signaling voltage on
the motherboard or VIO pin on the card edge of the
expansion card. The VIO pin will select the PCI
signaling level as indicated in Table 127. A 5 V refer-
ence voltage is not required for the USS-344 to be 5 V
compatible.
Table 127. PCI Signaling Levels
VIO Pin Input
Voltage
USS-344 PCI Signaling
Level (All PCI Signals)
4.75 V—5.25 V
3.0 V—3.6 V
5 V signaling
3.3 V signaling
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USS-344QUADRABUS | 制造商:AGERE 制造商全稱:AGERE 功能描述:Four-Host PCI-to-USB OpenHCI Host Controller |
| USS344S-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| USS-4(1m) | 制造商:Ubon 功能描述:1m 1 to 0.4mm D Bulk |
| USS4350 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
| USS4350G-AA3-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
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