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參數(shù)資料
| 型號： | USS-344 |
| 英文描述： | USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| 中文描述： | 號，344 QuadraBus四主機的PCI到USB主機控制器OpenHCL |
| 文件頁數(shù)： | 35/54頁 |
| 文件大?。?/td> | 850K |
| 代理商： | USS-344 |
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Agere Systems Inc.
35
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USS-344
QuadraBus
Legacy Support Registers
The legacy support function and all registers described in this section are available on all four embedded USB host
controllers. Four operational registers are used to provide the legacy support. Each of these registers is located on
a 32-bit boundary. The offset of these registers is relative to the base address of the respective host controller core
operational registers with HceControl located at offset 100h.
Table 121. Legacy Support Registers
Three of the operational registers (HceStatus, HceInput, HceOutput) are accessible at I/O address 60h and 64h
when emulation is enabled. Reads and writes to the registers using I/O addresses have side effects as outlined in
the Table 122.
Table 122. Emulated Registers
HceInput Register
Table 123. HceInput Register (104h)
I/O data that is written to ports 60h and 64h is captured in this register when emulation is enabled. This register
may be read or written directly by accessing it with its memory address in the host controller’s operational register
space. When accessed directly with a memory cycle, reads and writes of this register have no side effects.
Offset
100h
Register
HceControl
Description
Used to enable and control the emulation hardware and report various status
information.
Emulation side of the Legacy Input Buffer register.
Emulation side of the Legacy Output Buffer register where keyboard and
mouse data is to be written by software.
Emulation side of the Legacy Status register.
104h
108h
HceInput
HceOutput
10Ch
HceStatus
I/O
Address
60h
60h
Cycle
Type
IN
OUT
Register Contents
Accessed/Modified
HceOutput
HceInput
Side
Effects
IN from port 60h will set OutputFull in HceStatus to 0.
OUT to port 60h will set InputFull to 1 and CmdData to 0 in
HceStatus.
IN from port 64h returns current value of HceStatus with no
other side effect.
OUT to port 64h will set InputFull to 0 and CmdData in
HceStatus to 1.
64h
IN
HceStatus
64h
OUT
HceInput
Bit
7:0
31:8
Field
InputData
Reserved
R/W
R/W
—
Description
This register holds data that is written to I/O ports 60h and 64h.
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USS-344QUADRABUS | 制造商:AGERE 制造商全稱:AGERE 功能描述:Four-Host PCI-to-USB OpenHCI Host Controller |
| USS344S-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller |
| USS-4(1m) | 制造商:Ubon 功能描述:1m 1 to 0.4mm D Bulk |
| USS4350 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
| USS4350G-AA3-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR |
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