參數(shù)資料
型號： USS-344
英文描述： USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller
中文描述： 號，344 QuadraBus四主機(jī)的PCI到USB主機(jī)控制器OpenHCL
文件頁數(shù)： 42/54頁
文件大小： 850K
代理商： USS-344
42
Agere Systems Inc.
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USS-344
QuadraBus
Power Management Interface
An advanced power management capabilities interface compliant with
PCI Bus Power Management Interface
Specification Revision 1.1
has been incorporated into each of the USS-344 controllers. This interface allows the
USS-344 to be placed in various power management states offering a variety of power savings for a host system.
Table 129 highlights the USS-344 support for power management states and features supported for each of the
power management states. The USS-344 has the ability to internally gate-off the CLK48 input, disable the USB
transceivers, and assert USB resume signaling asynchronously (without active CLK48) in response to upstream
USB resume being detected. The USS-344 will assert PMEN and retain chip context in accordance with the rules
defined in the
PCI Bus Power Management Interface Specification Revision 1.1.
* Asynchronous resume logic active only when PME_Enable register bit is active.
A wakeup event (power management event) detected by a USB host controller is considered either an upstream
resume detected or a connect status change (device disconnecting/connecting) detected. Any of these events
detected by the USS-344 while the power management event is enabled will cause PMEN to be issued.
This power management feature is considered an extension of the PCI Specification and is only present when
enabled by the TEST1 input pin. While the TEST1 input pin is logic 0 (or ground), the power management function
is enabled, the Power Management registers and Capabilities Pointer register are accessible, and the PCI Config-
uration Space Status register, bit 4, will read as logic 1 (capabilities list present). While the TEST1 input pin is
logic 1, the power management function is disabled, the Power Management registers and Capabilities Pointer
register are inaccessible and read as 0h, and the PCI Configuration Space Status register, bit 4, will read as logic 0
(no capabilities list).
Table 129. USS-344 Support for Power Management States
Power
Management
State
State
Required/
Optional
Clk48
Active
Internally
CLK48
STOP
Active
USB
Trans-
ciever
Active
Async
Resume
Logic
Active
PMEN
Assert
Enabled
Chip
Context
Main-
tained
Comments
D0
Required
X
X
—
—
X
Fully awake backwards com-
patible state. All logic in full-
power mode.
Fully awake state with PCI
bus master capabilities turned
off by host. All logic in full-
power mode because of low
latency returning to D0 State.
USB sleep state with PCI bus
master capabilities turned off
by host. PCI clocks may be
turned off by the system.
Deep USB sleep state with
PCI bus master capabilities
turned off by host. PCI clocks
may be turned off by the sys-
tem.
Fully asleep backwards com-
patible state. All power turned
off. Reset required to recover
to D0 state. All downstream
devices disconnected
because of power loss.
D1
Optional
X
X
—
X
X
D2
Optional
—
—
X*
X
X
D3
hot
Required
—
X
—
X*
X
—
D3
cold
Required
—
—
—
—
—
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