參數(shù)資料
型號(hào)： USS-344
英文描述： USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller
中文描述： 號(hào)，344 QuadraBus四主機(jī)的PCI到USB主機(jī)控制器OpenHCL
文件頁(yè)數(shù)： 36/54頁(yè)
文件大小： 850K
代理商： USS-344
36
Agere Systems Inc.
Advance Data Sheet, Rev. 9
June 2001
Four-Host PCI-to-USB OpenHCI Host Controller
USS-344
QuadraBus
Legacy Support Registers
(continued)
HceOutput Register
Table 124. HceOutput Register (108h)
The data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is
enabled. On a read of this location, the OutputFull bit in HceStatus is set to 0.
HceStatus Register
Table 125. HceStatus Register (10Ch)
The contents of the HceStatus register are returned on an I/O Read of port 64h when emulation is enabled. Reads
and writes of port 60h and writes to port 64h can cause changes in this register. Emulation software can directly
access this register through its memory address in the host controller’s operational register space. Accessing this
register through its memory address produces no side effects.
Bit
7:0
Field
R/W
R/W
Description
OutputData
This register hosts data that is returned when an I/O read of port 60h is per-
formed by application software.
—
31:8
Reserved
—
Bit
0
Field
OutputFull
R/W
R/W
Description
The HC sets this bit to 0 on a read of I/O port 60h. If IRQEn is set and Aux-
OutputFull is set to 0, then an IRQ1 is generated as long as this bit is set to 1.
If IRQEn is set and AuxOutputFull is set to 1, then an IRQ12 is generated as
long as this bit is set to 1. While this bit is 0 and CharacterPending in Hce-
Control is set to 1, an emulation interrupt condition exists.
Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write
to address 60h or 64h. While this bit is set to 1 and emulation is enabled, an
emulation interrupt condition exists.
Nominally used as a system flag by software to indicate a warm or cold boot.
The HC sets this bit to 0 on an I/O write to port 60h and to 1 on an I/O write to
port 64h.
This bit reflects the state of the keyboard inhibit switch and is set if the key-
board is
not
inhibited.
IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and
the IRQEn bit is set.
Used to indicate a time-out.
Indicates parity error on keyboard/mouse data.
—
1
InputFull
R/W
2
3
Flag
R/W
R/W
CmdData
4
Inhibit Switch
R/W
5
AuxOutputFull
R/W
6
7
Time-out
Parity
Reserved
R/W
R/W
—
31:8
相關(guān)PDF資料
PDF描述
USSP0175 LOW COST - HIGH PERFORMANC3 VOLTAGE CONTROLLED OSCILLATOR
USSP2330 LOW COST - HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR
USSP2400 LOW COST - HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR
UT100E ASIC
UT100ER ASIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
USS-344QUADRABUS 制造商:AGERE 制造商全稱:AGERE 功能描述:Four-Host PCI-to-USB OpenHCI Host Controller
USS344S-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller
USS-4(1m) 制造商:Ubon 功能描述:1m 1 to 0.4mm D Bulk
USS4350 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR
USS4350G-AA3-R 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:50V, 5A NPN LOW VCE(SAT) TRANSISTOR
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*