參數(shù)資料
型號: USS-344
英文描述: USS-344 QuadraBus Four-Host PCI-to-USB OpenHCL Host Controller
中文描述: 號,344 QuadraBus四主機(jī)的PCI到USB主機(jī)控制器OpenHCL
文件頁數(shù): 38/54頁
文件大小: 850K
代理商: USS-344
USS-344
QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9
June 2001
38
Agere Systems Inc.
Connection Instructions
(continued)
USB Connection Instructions
The USS-344 is a port-powered OHCI host controller
(refer to OHCI specification) requiring an external
switchable power regulator to supply downstream USB
port power controlled by the USS-344. The power
regulator interface has been designed to interface
directly with commonly used USB power regulators
with very little additional circuitry. The PRTPWR[0, 1, 2,
3] output signal is used as the switch for the power
regulator. The PRTPWR[0, 1, 2, 3] signal must be boot-
strapped with a pull-up or pull-down resistor to select
the appropriate power switch polarity. Bootstrapping
with a pull-up resistor will select an active-low power
switch while bootstrapping with a pull-down will select
an active-high power switch. Figure 3 depicts a typical
board connection for both power regulator enable
polarities.
The PWRFLT[0, 1, 2, 3]N can be connected directly to
an active-low power fault regulator output to inform the
USS-344 of a USB port overcurrent condition.
DPLS[0, 1, 2, 3] and DMNS[0, 1, 2, 3] are related to the
integrated USB transceiver and are connected directly
to the USB port connector through a 28
—32
series
resistor for each signal. Figure 5 shows complete detail
of the USS-344 connection to USB.
CLK48 must be connected to a 48 MHz oscillator to
provide a suitable USB clock to the USS-344. If
CLK48STOP signal is used to disable the external
oscillator during D3 Power Management state,
CLK48STOP must be bootstrapped with a pull-up or
pull-down resistor to select the appropriate disable
polarity. Bootstrapping with a pull-up resistor will select
an active-low disable while bootstrapping with a pull-
down will select an active-high disable. Figure 4
depicts a typical board connection for both oscillator
enable polarities. CLK48STOP must be pulled to a
stable logic value with a resistor if CLK48STOP is not
used. Figure 4 also shows the typical board connection
when CLK48STOP is not used.
Test Mode Connection Instructions
TEST[3:0] input pins present various options and test
modes for the USS-344. These pins can be connected
directly to V
DD
or ground as needed. One test mode
(NAND tree mode) is available for a system designer to
implement. For a system designer who wishes to
implement NAND tree mode, it is recommended that a
pull-down resistor be used on TEST2 input. This will
allow an in-circuit tester to drive TEST2 high and acti-
vate NAND tree mode (see NAND Tree Mode section).
TEST3, TEST1, and TEST0 can be grounded without a
resistor.
It is also recommended that all NAND tree pins have a
corresponding PWB trace that can be driven by the in-
circuit tester during NAND tree mode.
Table 128. Test Mode Decodes
TEST[3:0]
00X0
Description
Share Interrupt A.
All four controllers
return a 01h in the Interrupt Pin register
(3Dh) and use the PCI interrupt A pin.
Individual Interrupt.
Controller 0 returns
01h in the Interrupt Pin register (3Dh)
and uses the PCI interrupt A pin.
00X1
Controller 1 returns 02h in the interrupt
pin register (3Dh) and uses the PCI inter-
rupt B pin.
Controller 2 returns 03h in the Interrupt
Pin register (3Dh) and uses the PCI inter-
rupt C pin.
Controller 3 returns 04h in the Interrupt
Pin register (3Dh) and uses the PCI inter-
rupt D pin.
Power Management Interface
Enabled.
Power management interface
enabled in all four controllers.
Power Management Interface
Disabled.
Power management interface
disabled in all four controllers.
NAND Test.
000X
001X
01XX
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