參數(shù)資料
型號: UPD61052
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER
中文描述: 馬鞍山集成電路MPEG2音頻/視頻編碼器
文件頁數(shù): 92/106頁
文件大?。?/td> 824K
代理商: UPD61052
Data Sheet S15082EJ4V0DS
92
μ
PD61051, 61052
(b)
Parallel bus interface: Ready mode
(1/2)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
CCS
CA5 to CA0 delay time
t
CAD
Vs falling edge of CCS
Do not care
-
-
-
ns
CCS
CWAIT delay time
t
CWAD1
Vs falling edge of CCS
CCS later than CRE/CWE
15
CCS
CWAIT ready time
t
CRDY
Vs falling edge of CCS
CCS later than CRE/CWE
175
ns
CA5 to CA0
CRE
delay time
t
ARD
Vs CA5 to CA0
20
ns
CCS
CRE
delay time
t
CRD
Vs falling edge of CCS
20
ns
CRE
CWAIT ready time
t
RRD
Vs falling edge of CRE
175
ns
CCS
CD7 to CD0 low-Z time
t
CDLD
Vs falling edge of CCS
Data not fixed
0
ns
CRE
CD7 to CD0 low-Z time
t
RDLD
Vs falling edge of CRE
Data not fixed
0
ns
CCS
CD7 to CD0 delay time
t
CDD
Vs falling edge of CCS
Data fixed
150
ns
CRE
CD7 to CD0 delay time
t
RDD
Vs falling edge of CRE
Data fixed
150
ns
CRE
CD7 to CD0 hold time
t
RDH
Vs rising edge of CRE
Earlier than rising edge of
CCS
0
ns
CRE
CA5 to CA0 hold time
t
RAH
Vs rising edge of CRE
27
ns
CRE
CCS
hold time
t
RCH
Vs rising edge of CRE
27
ns
CCS
CD7 to CD0 hold time
t
CDRH
Vs rising edge of CCS
Earlier than rising edge of
CRE
0
ns
CD7 to CD0
CWAIT ready
time
t
CDW
Vs CD7 to CD0 fixed
10
ns
CD7 to CD0 high-Z delay time
t
CDZD
Vs rising edge of CRE or CCS
12
ns
CA5 to CA0
CWE
delay time
t
AWD
Vs CA5 to CA0
28
ns
CCS
CWE
delay time
t
CWD
Vs falling edge of CCS
20
ns
CWE
CWAIT ready time
t
WRD
Vs falling edge of CWE
150
ns
CWE
CD7 to CD0 delay time
t
WDD
Vs falling edge of CWE
Until data fixed
30
ns
CWE
CD7 to CD0 hold time
t
WDH
Vs rising edge of CWE
7
ns
CWE
CA5 to CA0 hold time
t
WAH
Vs rising edge of CWE
27
ns
CWE
CCS
hold time
t
WCH
Vs rising edge of CWE
27
ns
CCS
CD7 to CD0 hold time
t
CDWH
Vs rising edge of CCS
0
ns
CRE
CWAIT release time
t
RWD2
Vs rising edge of CRE
0
15
ns
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