- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379500 > UPD61052 (NEC Corp.) MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER PDF資料下載
參數(shù)資料
| 型號： | UPD61052 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數(shù)： | 32/106頁 |
| 文件大小： | 824K |
| 代理商： | UPD61052 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
Data Sheet S15082EJ4V0DS
32
μ
PD61051, 61052
2.5
Host CPU Interface
The connection of the host CPU can select the eight bits parallel data interface and serial interface (SPI). Internal
CPU sends and receives command status through the System Interface Register, which is in the host CPU interface
unit. In addition, to control an internal DMA controller through the system interface register, it loads an instruction for
internal CPU to the instruction RAM and the transfer of the large-volume data can be sent to the data area on SDRAM.
Figure 2-12. Host CPU Interface
Host
CPU
System
Interface
Register
Instruction
RAM of
Internal CPU
Internal
CPU
SDRAM
Interface
SDRAM
DMA
Controller
μPD61051/61052
The following describes loading of internal CPU instruction.
(1)
Parallel interface
When parallel interface is selected, host interface has 6-bit address, 8-bit data bus and control ports.
CWAIT is selected with CMODE1 to wait on ready signal mode, CMODE1 selects active polarity of CWAIT.
(2)
Serial interface
The
μ
PD61051/61052 communicates with the host CPU using the SPI (serial peripheral interface) serial bus. The
host CPU becomes a bus master.
The low edge of the chip selection is communication beginning. Its high edge is communication ending.
An address and the reading / writing mode are shown at the first byte after the chip selection becomes low.
It is the MSB first of six bits of addresses, eight bits of data. Fix CSCLK to high level during CCS is disabled (high
level).
The
μ
PD61051/61052 becomes a master and downloads the instruction of the internal CPU from external ROM.
CSCLK:
The serial clock
CSDI:
The data input
CSDO:
The data output
CCS:
The chip selection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD61052GD-LML | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61052GD-LML-A | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD6376GS | TP Series Rocker Switch, 2 pole, 3 position, IWTS (14-16 Gage) terminal, Above Panel Mounting |
| UPD6376 | AUDIO 2-CHANNEL 16-BIT D/A CONVERTER |
| UPD7001 | 8-BIT CMOS SERIAL I/O ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD61052GD-LML | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD61052GD-LML-A | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| UPD6105C002 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| UPD61171 | 制造商:NEC 制造商全稱:NEC 功能描述:SECOND GENERATION ENHANCED MULTIMEDIA ARCHITECTURE PROCESSOR FOR DVD RECORDER/PERSONAL VIDEO RECORDERS |
| UPD61171F1-XYZ-MN2-A | 制造商:NEC 制造商全稱:NEC 功能描述:SECOND GENERATION ENHANCED MULTIMEDIA ARCHITECTURE PROCESSOR FOR DVD RECORDER/PERSONAL VIDEO RECORDERS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。