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參數(shù)資料
| 型號(hào)： | UPD61052 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁(yè)數(shù)： | 12/106頁(yè) |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052 |
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Data Sheet S15082EJ4V0DS
12
μ
PD61051, 61052
1.8
Host CPU Interface
It chooses a parallel bus connection and a serial bus connection by the setting of CMODE2.
Name
IO
Pin
Number
Function
Active
Polarity
CMODE2
I
158
Host CPU interface select
L: Parallel, H: Serial
1.8.1
Parallel bus interface
Name
IO
Pin Number
Function
Active
Polarity
CA5 to CA0
/
FA5 to FA0
I
187, 185 to 181
Address
CD7 to CD0
/
FD7 to FD0
IO
172, 170 to
166, 164, 162
Data
CWE
/CSDI
I
157
Write enable
L
CRE
I
160
Read enable
L
CCS
I
159
Chip selection
L
CINT
O
153
Interrupt
H
CWAIT
/FOE
O
161
Wait
CMODE0
/CSCLK
I
155
Setting of polarity of CWAIT
L: Low wait, H: High wait
CMODE1
/CSDO
I
156
Setting of operation of CWAIT
(Built-in 50 k
pull up resistor)
L: Wait operation.(after ready, pin continues ready)
H: Ready operation.(after ready, pin turns to wait)
1.8.2
Serial bus interface
When connecting a serial bus, it downloads instruction of internal CPU from instruction ROM.
(1)
Serial bus interface
Name
IO
Pin
Number
Function
Active
Polarity
CMODE0/
CSCLK
I
155
SPI serial interface clock
Fix CSCLK to high level during CCS is disable (high level).
↑
CWE/
CSDI
I
157
SPI serial interface data input
CMODE1/
CSDO
O
156
SPI serial interface data output
(Built-in 50 k
pull up resistor)
CCS
I
159
Chip selection
L
CINT
O
153
Interrupt
H
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