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參數(shù)資料
| 型號(hào)： | UPD61052 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁(yè)數(shù)： | 52/106頁(yè) |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052 |
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Data Sheet S15082EJ4V0DS
52
μ
PD61051, 61052
4.2
Firmware Download
The host CPU downloads the firmware at the instruction RAM for the internal CPU.
When a host CPU is connected with the serial bus, the firmware can be downloaded from the external ROM for the
download processing to speed up. In addition, it stores more than one piece of firmware in the instruction pool area of
SDRAM and it can be replaced depending on the need, too.
When transferring to the instruction RAM of the internal CPU, the transfer counter register setting value (number of
the transfer bytes / 4) is (program size +3)/ 4.
4.2.1
Host CPU to instruction RAM of internal CPU
Host CPU transmits the firmware to instruction RAM of the internal CPU.
When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can
canceled on the way, the internal CPU sometime malfunction.
Y
N
Return
Host CPU
to instruction RAM
of internal CPU
Internal CPU reset
Reset register (3EH)
←
02H setting
Destination address register
(24H to 26H) setting
(Program size + 3)/4
Transfer counter register
(27H to 29H) setting
Host CPU
→
iRAM transfer
Transfer mode register
(20H)
←
80H setting
Transfer data register
(3FH)
←
Instruction
Transfer ending (refer to
4.7
)
All instruction written
Internal CPU reset is canceled
Reset register
(3EH)
←
00H setting
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