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參數(shù)資料
| 型號： | UPD61052 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數(shù)： | 50/106頁 |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052 |
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Data Sheet S15082EJ4V0DS
50
μ
PD61051, 61052
4.
SYSTEM INTERFACE PROCEDURE
The host CPU transfers the firmware of each operation mode to the instruction RAM of the internal CPU and works
it.
This LSI stores up firmware in SDRAM. Host CPU sets to load the firmware of each operation mode in the
instruction RAM of internal CPU from SDRAM.
When using a parallel bus interface for the host CPU interface, the host CPU sets a data transfer register after
hardware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU and executing.
Host CPU writes firmware to SDRAM.
When using a serial bus interface for the host CPU interface, the host CPU sets a data transfer register after
hardware ware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU from
external instruction ROM and executing. Host CPU loads firmware in SDRAM from instruction ROM outside.
It stores the firmware of the encoding and the transcode to SDRAM from ROM in case of start-up of the system,
and then it can do the changing of a feature at short time by the high-speed transfer of SDRAM.
The host CPU sets the mode of the terminal of the
μ
PD61051/61052 and the access cycle of ROM to the system
interface register after hardware reset and sets the transfer of the instruction of the internal CPU after SDRAM is
initialized.
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