參數(shù)資料
型號： UPD61052
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER
中文描述： 馬鞍山集成電路MPEG2音頻/視頻編碼器
文件頁數(shù)： 7/106頁
文件大小： 824K
代理商： UPD61052
Data Sheet S15082EJ4V0DS
7
μ
PD61051, 61052
CONTENTS
1. PIN FUNCTION ............................................................................................................................... 9
1.1
Video Input Interface.............................................................................................................................9
1.2
Video Output Interface..........................................................................................................................9
1.3
Audio Input Interface ............................................................................................................................9
1.4
Audio Input/output Interface ..............................................................................................................10
1.5
Stream Input Interface ........................................................................................................................10
1.6
Stream Output Interface .....................................................................................................................11
1.7
SDRAM Interface.................................................................................................................................11
1.8
Host CPU Interface..............................................................................................................................12
1.8.1 Parallel bus interface.................................................................................................................12
1.8.2 Serial bus interface....................................................................................................................12
1.9
Clock, Reset.........................................................................................................................................13
1.10 N-Wire...................................................................................................................................................13
1.11 GPIO.....................................................................................................................................................14
1.12 Power Supply ......................................................................................................................................14
1.13 Recommended Connections of Unused Pins...................................................................................15
2. FEATURE OVERVIEW.................................................................................................................. 16
2.1
Video ....................................................................................................................................................16
2.1.1 Encoding ...................................................................................................................................16
2.1.2 Transcoding...............................................................................................................................16
2.1.3 Input/output processing.............................................................................................................17
2.2
Audio....................................................................................................................................................19
2.2.1 Encoding ...................................................................................................................................19
2.2.2 Transcoding (DEMUX, MUX) ....................................................................................................19
2.2.3 Input/output processing.............................................................................................................19
2.3
MPEG System Processing..................................................................................................................22
2.3.1 System time clock .....................................................................................................................22
2.3.2 Multiplex....................................................................................................................................23
2.3.3 De-multiplex ..............................................................................................................................23
2.3.4 Transcode .................................................................................................................................24
2.4
Stream Interface..................................................................................................................................25
2.4.1 Parallel steam data interface.....................................................................................................25
2.4.2 Serial stream data interface.......................................................................................................29
2.5
Host CPU Interface..............................................................................................................................32
2.6
SDRAM Interface.................................................................................................................................33
2.7
Memory Connection Diagram ............................................................................................................34
2.8
Memory Map ........................................................................................................................................36
3. SYSTEM INTERFACE REGISTER.............................................................................................. 38
3.1
Register Mapping (General Mapping)................................................................................................39
3.2
Register Functions..............................................................................................................................40
3.2.1 Common register.......................................................................................................................40
3.2.2 Data transfer register.................................................................................................................40
3.2.3 Internal CPU interrupt register...................................................................................................47
3.2.4 Interrupt mask register ..............................................................................................................47
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